MT8920BC Zarlink Semiconductor, MT8920BC Datasheet - Page 5

• Manufacturer Part Number: MT8920BC
• Description: MT8920 - 32 Channels TDM (ST-BUS) to Parallel Bus Access Circuit
• Manufacturer: Zarlink Semiconductor

Data Sheet
24/32 Channel Operation
The STPA may be configured to operate as a 32
channel or 24 channel device. This feature, which is
available in all three modes of operation, is
particularly useful in applications involving data
access to CEPT and T1 digital trunk interfaces.
When used as a data interface to Zarlink‘s CEPT
digital trunks, the STPA maps the 32 consecutive
bytes of each dual port memory directly to ST-BUS
channels 0-31. This is performed by the address
generator shown in the functional block diagram (see
Figure 1). Figures 4 c & d show the relationship
between relative dual port RAM locations and
corresponding ST-BUS channels, for both input and
output serial streams, when the STPA is configured
as a 32 channel device.
When used as a data interface to Zarlink’s T1 trunk
devices, however, only the first 24 consecutive RAM
locations are mapped to 24 of the 32 ST-BUS
channels. This mapping follows a specific pattern
which corresponds with the data streams used by
Zarlink‘s T1 products. Instead of a direct correlation
(as in 32 channel operation), the 24 consecutive
RAM locations are mapped to the ST-BUS with every
fourth channel, beginning at channel 0, set to FF
(ie. channel 0, 4, 8, 12, 16, 20, 24 and 28). Figures
4 a & b show the relationship between RAM
locations and ST-BUS channel configuration. This
feature allows the STPA to be interfaced directly to
Zarlink’s T1 trunk family.
When the STPA is operated in Mode 1, 24 and 32
channel configurations are selected using bit D
(RAMCON) in Control Register 1. D
channel operation and D
operation. When the STPA is operated in Modes 2
or 3, however, the channel configuration is done
using input 24/32 (pin 25). When 24/32 = 1 the
device uses all 32 channels and when 24/32 = 0 it
uses 24.
Dual Port RAMS
Each of the three serial ST-BUS streams is
interfaced to the parallel bus through a 32 byte dual
port RAM. This allows parallel bus accesses to be
performed asynchronously while accesses at the
ST-BUS port are synchronous with ST-BUS clock.
As with any dual port RAM interface between two
asynchronous systems, the possibility of access
contention
occurrence by recognizing contention only when
accesses are performed at the same time for the
same 8-bit cell within the dual port RAM’s.
Furthermore,
exists.
the
probability
The
5
= 1 selects 24 channel
STPA
of
minimizes
5
contention
= 0 selects 32
this
16
is
5
lessened since ST-BUS accesses require only the
last half cycle of C4i of every channel.
contention does occur, priority is always given to the
ST-BUS access.
The STPA indicates this contention situation in a
different manner for Modes 1 and 2. In Mode 1, the
contention is masked by virtue of the "handshaking"
method used to transfer data on this 68000-type
interface.
Acknowledge (DTACK) control
contention
returning DTACK and thus stretch the bus cycle until
the µP access can be completed.
In Mode 2, if access is attempted during a
"contention window" the STPA will supply
BUSY signal to delay the start of the bus cycle.
“contention window” is defined as shown in Figure
16. The window exists during the last cycle of C4i
clock in each channel timeslot.
access is only required during the last half of this
clock period, the “contention window“ exists for the
entire clock period since a parallel access occurring
just prior to an ST-BUS access will not complete
before the ST-BUS access begins. Figure 16 further
shows four possible situations that may occur when
parallel accesses are attempted in and around the
“contention window”. Condition 1 indicates that an
access occurring prior to the contention window but
lasting into the first half of it will complete normally
with no contention arbitration. If the access should
extend past the first half of the contention window
and into the ST-BUS access period, the BUSY signal
will be generated. Conditions 3 and 4 show accesses
occurring inside
accesses will result in BUSY becoming active
immediately after the access is initiated and
remaining active as shown in Figure 16.
Access contention is non-existent in Mode 3 since
the parallel bus signals, driven by the STPA, are
synchronized to the ST-BUS clocks.
Mode 1 - µP Peripheral Mode
In Mode 1, the STPA operates as an asynchronous
68000-type microprocessor peripheral.
dual-port RAMS (Tx0, Tx1, Rx0) are made available
and may be configured as 32 or 24 byte RAM’s. Also
available are the full complement of control and
interrupt registers. The address map for Mode 1 is
shown in Table 2.
The STPA, in Mode 1, uses signals CS, R/W, DS
(Data Strobe), DTACK (Data Acknowledge) IRQ, and
IACK (Interrupt Acknowledge) at the parallel interface.
The pinout of the device is shown in Figure 3.
should
Data Strobe (DS) and Data Transfer
the contention window. These
occur
the
the exchange.
Although ST-BUS
device will delay
MT8920B
All three
When
This
the
If
5