ADC1175CIMTC National Semiconductor, ADC1175CIMTC Datasheet - Page 15

• Manufacturer Part Number: ADC1175CIMTC
• Description: 8-Bit/ 20MHz/ 60mW A/D Converter
• Manufacturer: National Semiconductor

digital signal lines and away from power supply currents. This
latter requirement requires the careful separation and place-
ment of power planes. The use of power traces rather than
one or more power planes is not recommended as higher fre-
quencies are not well filtered with lumped capacitances. To
filter higher frequency noise components it is necessary to
have sufficient capacitance between the power and ground
planes.
If separate analog and digital ground planes are used, the
analog and digital grounds may be in the same layer, but
should be separated from each other. If separate analog and
digital ground layers are used, they should never overlap
each other.
Capacitive coupling between a typically noisy digital ground
plane and the sensitive analog circuitry can lead to poor per-
formance that may seem impossible to isolate and remedy.
The solution is to keep the analog circuity well separated from
the digital circuitry.
Digital circuits create substantial supply and ground current
transients. The logic noise thus generated could have signif-
icant impact upon system noise performance. The best logic
family to use in systems with A/D converters is one which
employs non-saturating transistor designs, or has low noise
characteristics, such as the 74HC(T) and 74AC(T)Q families.
The worst noise generators are logic families that draw the
largest supply current transients during clock or signal edges,
like the 74F and the 74AC(T) families. In general, slower logic
families will produce less high frequency noise than do high
speed logic families.
Since digital switching transients are composed largely of
high frequency components, total ground plane copper
weight will have little effect upon the logic-generated noise.
This is because of the skin effect. Total surface area is more
important than is total ground plane volume.
An effective way to control ground noise is by using a single,
solid ground plane, splitting the power plane into analog and
digital areas and having power and ground planes in adjacent
board layers. There should be no traces within either the
power or the ground layers of the board. The analog and dig-
ital power planes should reside in the same board layer so
that they can not overlap each other. The analog and digital
power planes define the analog and digital areas of the board.
Generally, analog and digital lines should cross each other at
90 degrees to avoid getting digital noise into the analog path.
In high frequency systems, however, avoid crossing analog
and digital lines altogether. Clock lines should be isolated
from ALL other lines, analog and digital. Even the generally
accepted 90 degree crossing should be avoided as even a
little coupling can cause problems at high frequencies. Best
performance at high frequencies and at high resolution is ob-
tained with a straight signal path.
Be especially careful with the layout of inductors. Mutual in-
ductance can change the characteristics of the circuit in which
they are used. Inductors should not be placed side by side,
not even with just a small part of their bodies being beside
each other.
The analog input should be isolated from noisy signal traces
to avoid coupling of spurious signals into the input. Any ex-
ternal component (e.g., a filter capacitor) connected between
the converter's input and ground should be connected to a
very clean point in the ground return.
6.0 DYNAMIC PERFORMANCE
The ADC1175 is a.c. tested and its dynamic performance is
guaranteed. To meet the published specifications, the clock
source driving the CLK input must be free of jitter. For best
15
a.c. performance, isolating the ADC clock from any digital cir-
cuitry should be done with adequate buffers, as with a clock
tree. See Figure 6.
FIGURE 6. Isolating the ADC clock from Digital Circuitry.
It is good practice to keep the ADC clock line as short as pos-
sible and to keep it well away from any other signals. Other
signals can introduce jitter into the clock signal.
7.0 COMMON APPLICATION PITFALLS
Driving the inputs (analog or digital) beyond the power
supply rails. For proper operation, all inputs should not go
more than 50mV below the ground pins or 50mV above the
supply pins. Exceeding these limits on even a transient basis
can cause faulty or erratic operation. It is not uncommon for
high speed digital circuits to exhibit undershoot that goes
more than a volt below ground due to improper line termina-
tion. A resistor of 50Ω to 100Ω in series with the offending
digital input, located close to the signal source, will usually
eliminate the problem.
Care should be taken not to overdrive the inputs of the
ADC1175. Such practice may lead to conversion inaccura-
cies and even to device damage.
Attempting to drive a high capacitance digital data bus.
The more capacitance the output drivers must charge for
each conversion, the more instantaneous digital current is re-
quired from DV
spikes can couple into the analog section, degrading dynamic
performance. Buffering the digital data outputs (with an
74AC541, for example) may be necessary if the data bus to
be driven is heavily loaded. Dynamic performance can also
be improved by adding 47Ω to 100Ω series resistors at each
digital output, reducing the energy coupled back into the con-
verter output pins.
Using an inadequate amplifier to drive the analog input.
As explained in Section 1.0, the capacitance seen at the input
alternates between 4 pF and 11 pF with the clock. This dy-
namic capacitance is more difficult to drive than is a fixed
capacitance, and should be considered when choosing a
driving device. The LMH6702, LMH6609, LM6152, LM6154,
LM6181 and LM6182 have been found to be excellent de-
vices for driving the ADC1175 analog input.
Driving the V
not source or sink the current required by the ladder. As
mentioned in section 2.0, care should be taken to see that any
driving devices can source sufficient current into the V
and sink sufficient current from the V
not driven with devices than can handle the required current,
these reference pins will not be stable, resulting in a reduction
of dynamic performance.
Using a clock source with excessive jitter, using an ex-
cessively long clock signal trace, or having other signals
coupled to the clock signal trace. This will cause the sam-
RT
DD
pin or the V
and DGND. These large charging current
RB
pin with devices that can
RB
pin. If these pins are
www.national.com
10009217
RT
pin