MT2LDT832H Micron Technology, MT2LDT832H Datasheet - Page 2

• Manufacturer Part Number: MT2LDT832H
• Description: (MT2LDT432H / MT2LDT832H) SMALL-OUTLINE DRAM MODULE
• Manufacturer: Micron Technology

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DataSheet
GENERAL DESCRIPTION
are randomly accessed 16MB and 32MB memories
organized in a small-outline x32 configuration. They
are specially processed to operate from 3V to 3.6V for
low-voltage memory systems.
addressed through the address bits, which are entered
12 bits (A0-A11) at a time. RAS# is used to latch the first
12 bits and CAS# the latter 10 bits.
input. A logic HIGH on WE# dictates read mode, while
a logic LOW on WE# dictates write mode. During a
WRITE cycle, data-in (D) is latched by the falling edge
of WE# or CAS#, whichever occurs last. If WE# goes
LOW prior to CAS# going LOW, the output pin(s)
remain open (High-Z) until the next CAS# cycle.
FAST PAGE MODE
operations (READ or WRITE) within a row-address-
defined page boundary. The FAST-PAGE-MODE cycle
is always initiated with a row address strobed in by
RAS#, followed by a column address strobed in by
CAS#. Additional columns may be accessed by provid-
ing valid column addresses, strobing CAS# and hold-
ing RAS# LOW, thus executing faster memory cycles.
Returning RAS# HIGH terminates the FAST-PAGE-
MODE operation.
EDO PAGE MODE
is an accelerated FAST-PAGE-MODE cycle. The pri-
mary advantage of EDO is the availability of data-out
even after CAS# goes back HIGH. EDO provides for
CAS# precharge time (
put data going invalid. This elimination of CAS#
output control provides for pipelined READs.
turned the output buffers off (High-Z) with the rising
edge of CAS#. EDO operates as any DRAM READ or
4, 8 Meg x 32 DRAM SODIMMs
DM89.p65 – Rev. 12/98
4
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The MT2LDT432H (X)(S) and MT4LDT832H (X)(S)
During READ or WRITE cycles, each bit is uniquely
READ and WRITE cycles are selected with the WE#
FAST-PAGE-MODE operations allow faster data
EDO PAGE MODE, designated by the “X” version,
FAST-PAGE-MODE modules have traditionally
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CP) to occur without the out-
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FAST-PAGE-MODE READ, except data will be held
valid or become valid after CAS# goes HIGH, as long as
RAS# and OE# are held LOW. (Refer to the 4 Meg x 16
[MT4LC4M16R6] DRAM data sheet for additional
information on EDO functionality.)
REFRESH
maintaining power and executing any RAS# cycle
(READ, WRITE) or RAS# refresh cycle (RAS#-ONLY,
CBR or HIDDEN) so that all combinations of RAS#
addresses are executed at least every
sequence. The CBR REFRESH cycle will invoke the
internal refresh counter for automatic RAS# address-
ing.
“S” option allows the user the choice of a fully static,
low-power data retention mode or a dynamic refresh
mode at the extended refresh period of 128ms. The
optional self refresh feature is initiated by performing
a CBR REFRESH cycle and holding RAS# LOW for the
specified
HIGH for a minimum time of
for the completion of any internal refresh cycles that
may be in process at the time of the RAS# LOW-to-
HIGH transition. If the DRAM controller uses a distrib-
uted refresh sequence, a burst refresh is not required
upon exiting self refresh. However, if the DRAM con-
troller utilizes a RAS#-ONLY or burst refresh sequence,
all rows must be refreshed within the average internal
refresh rate, prior to the resumption of normal opera-
tion.
STANDBY
memory cycle and decreases chip current to a reduced
standby level. Also, the chip is preconditioned for the
next cycle during the RAS# HIGH time.
Memory cell data is retained in its correct state by
An optional self refresh mode is also available. The
The self refresh mode is terminated by driving RAS#
Returning RAS# and CAS# HIGH terminates a
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
RASS.
DRAM SODIMMs
4, 8 MEG x 32
t
RPS. This delay allows
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REF, regardless of
©1998, Micron Technology, Inc.
ADVANCE
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