MT90823 Zarlink Semiconductor, MT90823 Datasheet - Page 12

• Manufacturer Part Number: MT90823
• Description: 3V Large Digital Switch
• Manufacturer: Zarlink Semiconductor

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For multiplexed operation, the 8-bit data and address (AD0-AD7), 8-bit Data (D8-D15), Address strobe/Address
latch enable (AS/ALE), Data strobe/Read (DS/RD), Read/Write /Write (R/W / WR), Chip select (CS) and Data
transfer acknowledge (DTA) signals are required. See Figure 13 and Figure 14 for multiplexed parallel microport
timing.
For the Motorola non-multiplexed bus, the 16-bit data bus (AD0-AD7, D8-D15), 8-bit address bus (A0-A7) and 4
control lines (CS, DS, R/W and DTA) signals are required. See Figure 15 for Motorola non- multiplexed microport
timing.
The MT90823 microport provides access to the internal registers, connection and data memories. All locations
provide read/write access except for the data memory and the frame alignment register which are read only.
Memory Mapping
The address bus on the microprocessor interface selects the MT90823 internal registers and memory. If the A7
address input is low, then the control (CR), interface mode selection (IMS), frame alignment (FAR) and frame input
offset (FOR) registers are addressed by A6 to A0 as shown in Table 4.
If the A7 address input is high, then the remaining address input lines are used to select up to 128 memory
subsection locations. The number selected corresponds to the maximum number of channels per input or output
stream. The address input lines and the stream address bits (STA) of the control register allow access to the entire
data and connection memories.
The control and IMS registers together control all the major functions of the device. The IMS register should be
programmed immediately after system power-up to establish the desired switching configuration (see “Serial Data
Interface Timing” and “Switching Configurations” ).
The control register controls switching operations in the MT90823. It selects the internal memory locations that
specify the input and output channels selected for switching.
The data in the control register consists of the memory block programming bit (MBP), the memory select bit (MS)
and the stream address bits (STA). The memory block programming bit allows users to program the entire
connection memory block, (see “Memory Block Programming” ). The memory select bit controls the selection of the
connection memory or the data Memory. The stream address bits define an internal memory subsections
corresponding to input or output ST-BUS streams.
The data in the IMS register consists of block programming bits (BPD0-BPD4), block programming enable bit
(BPE), output standby bit (OSB), start frame evaluation bit (SFE) and data rate selection bits (DR0, DR1). The block
programming and the block programming enable bits allows users to program the entire connection memory, (see
Memory Block Programming section). If the ODE pin is low, the OSB bit enables (if high) or disables (if low) all ST-
BUS output drivers. If the ODE pin is high, the contents of the OSB bit is ignored and all ST-BUS output drivers are
enabled.
MT90823
Input Rate
2.048 Mb/s
4.096 Mb/s
8.192 Mb/s
Table 3 - Constant Throughput Delay Value
Zarlink Semiconductor Inc.
Delay for Constant Throughput Delay Mode
128 + (128 - n) + (m- 1) time-slots
32 + (32 - n) + (m - 1) time-slots
64 + (64 - n) + (m- 1) time-slots
(m - output channel number)
(n - input channel number))
Data Sheet