MT90823 Zarlink Semiconductor, MT90823 Datasheet - Page 22

• Manufacturer Part Number: MT90823
• Description: 3V Large Digital Switch
• Manufacturer: Zarlink Semiconductor

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JTAG Support
The MT90823 JTAG interface conforms to the IEEE 1149.1 Boundary-Scan standard and the Boundary-Scan Test
(BST) design-for-testability technique it specifies. The operation of the boundary-scan circuitry is controlled by an
external test access port (TAP) Controller.
Test Access Port (TAP)
The Test Access Port (TAP) provides access to the many test functions of the MT90823. It consists of three input
pins and one output pin. The following pins comprise the TAP.
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Instruction Register
In accordance with the IEEE 1149.1 standard, the MT90823 uses public instructions. The MT90823 JTAG Interface
contains a three-bit instruction register. Instructions are serially loaded into the instruction register from the TDI
when the TAP Controller is in its shifted-IR state. Subsequently, the instructions are decoded to achieve two basic
functions: to select the test data register that may operate while the instruction is current, and to define the serial
test data register path, which is used to shift data between TDI and TDO during data register scanning.
MT90823
Test Clock Input (TCK)
TCK provides the clock for the test logic. The TCK does not interfere with any on-chip clock and thus
remains independent. The TCK permits shifting of test data into or out of the Boundary-Scan register cells
concurrently with the operation of the device and without interfering with the on-chip logic.
Test Mode Select Input (TMS)
The logic signals received at the TMS input are interpreted by the TAP Controller to control the test
operations. The TMS signals are sampled at the rising edge of the TCK pulse. This pin is internally pulled to
Vdd when it is not driven from an external source.
Test Data Input (TDI)
Serial input data applied to this port is fed either into the instruction register or into a test data register,
depending on the sequence previously applied to the TMS input. Both registers are described in a
subsequent section. The received input data is sampled at the rising edge of TCK pulses. This pin is
internally pulled to Vdd when it is not driven from an external source.
Test Data Output (TDO)
Depending on the sequence previously applied to the TMS input, the contents of either the instruction
register or data register are serially shifted out towards the TDO. The data out of the TDO is clocked on the
falling edge of the TCK pulses. When no data is shifted through the boundary scan cells, the TDO driver is
set to a high impedance state.
Test Reset (TRST)
Resets the JTAG scan structure. This pin is internally pulled to VDD.
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