MT90823 Zarlink Semiconductor, MT90823 Datasheet - Page 9

• Manufacturer Part Number: MT90823
• Description: 3V Large Digital Switch
• Manufacturer: Zarlink Semiconductor

Data Sheet
The MT90823 provides two different interface timing modes controlled by the WFPS pin. If the WFPS pin is low, the
MT90823 is in ST-BUS/GCI mode. If the WFPS pin is high, the MT90823 is in the wide frame pulse (WFP) frame
alignment mode.
In ST-BUS/GCI mode, the input 8 kHz frame pulse can be in either ST-BUS or GCI format. The MT90823
automatically detects the presence of an input frame pulse and identifies it as either ST-BUS or GCI. In ST-BUS
format, every second falling edge of the master clock marks a bit boundary and the data is clocked in on the rising
edge of CLK, three quarters of the way into the bit cell, see Figure 11. In GCI format, every second rising edge of
the master clock marks the bit boundary and data is clocked in on the falling edge of CLK at three quarters of the
way into the bit cell, see Figure 12.
Wide Frame Pulse (WFP) Frame Alignment Timing
When the device is in WFP frame alignment mode, the CLK input must be at 16.384 MHz, the FE/HCLK input is
4.096 MHz and the 8 kHz frame pulse is in ST-BUS format. The timing relationship between CLK, HCLK and the
frame pulse is defined in Figure 13.
When the WFPS pin is high, the frame alignment evaluation feature is disabled, but the frame input offset registers
may still be programmed to compensate for the varying frame delays on the serial input streams.
Switching Configurations
The MT90823 maximum non-blocking switching configurations is determined by the data rates selected for the
serial inputs and outputs. The switching configuration is selected by two DR bits in the IMS register. See Table 8 nd
Table 9.
2.048 Mb/s Serial Links (DR0=0, DR1=0)
When the 2.048 Mb/s data rate is selected, the device is configured with 16-input/16-output data streams each
having 32 64 kb/s channels. This mode requires a CLK of 4.094 MHz and allows a maximum non-blocking capacity
of 512 x 512 channels.
4.096 Mb/s Serial Links (DR0=1, DR1=0)
When the 4.096 Mb/s data rate is selected, the device is configured with 16-input/16-output data streams each
having 64 64 kb/s channels. This mode
capacity of 1,024 x 1,024 channels.
8.192 Mb/s Serial Links (DR0=0, DR1=1)
When the 8.192 Mb/s data rate is selected, the device is configured with 16-input/16-output data streams each
having 128 64 kb/s channels. This mode requires a CLK of 16.384 MHz and allows a maximum non-blocking
capacity of 2,048 x 2,048 channels. Table 1 summarizes the switching configurations and the relationship between
different serial data rates and the master clock frequencies.
Serial Interface
Data Rate
2 Mb/s
4 Mb/s
8 Mb/s
Table 1 - Switching Configuration
requires a CLK of 8.192 MHz and allows a maximum non-blocking
Zarlink Semiconductor Inc.
Required (MHz)
Master Clock
16.384
4.096
8.192
Matrix Channel
1,024 x 1,024
2,048 x 2,048
512 x 512
Capacity
MT90823
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