MT90823 Zarlink Semiconductor, MT90823 Datasheet - Page 5

• Manufacturer Part Number: MT90823
• Description: 3V Large Digital Switch
• Manufacturer: Zarlink Semiconductor

Data Sheet
Pin Description (continued)
PLCC
41 -
84
35
36
37
38
39
40
48
49
MQFP
14-21
100
10
12
13
22
11
8
9
LQFP
100
11 -
Pin #
10
18
19
9
5
6
7
8
M8,N9,M9,N10
N6,M7,N7,N8,
BGA
N11
120
N3
M4
N4
M5
N5
M6
Zarlink Semiconductor Inc.
RESET
A0 - A7
DS/RD
WFPS
Name
TRST
TDO
TCK
IC
Test Serial Data Out (3.3V Output): JTAG serial data
is output on this pin on the falling edge of TCK. This pin
is held in high impedance state when JTAG scan is not
enabled.
Test Clock (5V Tolerant Input): Provides the clock to
the JTAG test logic.
Test Reset (3.3V Input with internal pull-up):
Asynchronously initializes the JTAG TAP controller by
putting it in the Test-Logic-Reset state. This pin should
be pulsed low on power-up, or held low, to ensure that
the MT90823 is in the normal functional mode.
Internal Connection (3.3V Input with internal pull-
down): Connect to V
must be low for the MT90823 to function normally and
to comply with IEEE 1149 (JTAG) boundary scan
requirements.
Device Reset (5V Tolerant Input): This input (active
LOW) puts the MT90823 in its reset state to clear the
device internal counters, registers and bring STo0 - 15
and microport data outputs to a high impedance state.
The time constant for a power up reset circuit must be a
minimum of five times the rise time of the power supply.
In normal operation, the RESET pin must be held low
for a minimum of 100nsec to reset the device.
Wide Frame Pulse Select (5V Tolerant Input): When
1, enables the wide frame pulse (WFP) Frame
Alignment interface. When 0, the device operates in
ST-BUS/GCI mode.
Address 0 - 7 (5V Tolerant Input): When non-
multiplexed CPU bus operation is selected, these lines
provide the A0 - A7 address lines to the internal
memories.
Data Strobe / Read (5V Tolerant Input): For Motorola
multiplexed bus operation, this input is DS. This active
high DS input works in conjunction with CS to enable
the read and write operations.
For Motorola non-multiplexed CPU bus operation, this
input is DS. This active low input works in conjunction
with CS to enable the read and write operations.
For multiplexed bus operation, this input is RD. This
active low input sets the data bus lines (AD0-AD7, D8-
D15) as outputs.
SS
Description
for normal operation. This pin
MT90823
5