MT90871 Zarlink Semiconductor, MT90871 Datasheet - Page 21

• Manufacturer Part Number: MT90871
• Description: Flexible 8K Digital Switch (F8KDX)
• Manufacturer: Zarlink Semiconductor

Data Sheet
outputs. Setting BORS to a HIGH state will configure the output streams BSTo0-15 of the MT90871 to invoke
a high-impedance output on a per-channel basis.
The BORS pin is an asynchronous input and is expected to be hard-wired for a particular system application,
although it may be driven under logic control if preferred.
4.2.1
The data (channel control bit) transmitted by BCSTo0-1 replicates the Backplane Output Enable Bit (BE) of
the Backplane Connection Memory, with a LOW state indicating that the channel should be set to High
Impedance by external drivers. Refer to section 12.4 "Backplane Connection Memory Bit Definition".
The BCSTo0-1 outputs transmit serial data (channel control bits) at 16.384Mb/s, with each bit representing the
per-channel high impedence state for specific streams. Eight output streams are allocated to each control line
as follows:
•
•
(See also Pin Description)
The Channel Control Bit location, within a frame period, for each channel of the Backplane output streams is
presented in Table 3, BCSTo Allocation of Channel Control Bits to the Output Streams.
As an aid to the description, the channel control bit for a single channel on specific streams is presented, with
reference to Table 3:
1.
2.
The BCSTo0-1 outputs data at a constant data-rate of 16.384Mb/s, independent of the data-rate selected for
the individual output streams, BSTo0-15. Streams at data-rates lower than 16.384Mb/s will have the value of
the respective channel control bit repeated for the duration of the channel. The bit will be transmitted twice for
8.192Mb/s streams, four times for 4.096Mb/s streams and eight times for 2.048Mb/s streams. The channel
control bit is not repeated for 16.384Mb/s streams.
Examples are presented, with reference to Table 3:
3.
4.
BCSTo0 outputs the channel control bits for streams BSTo0, 2, 4, 6, 8, 10, 12 and 14.
BCSTo1 outputs the channel control bits for streams BSTo1, 3, 5, 7, 9, 11, 13 and 15.
The Channel Control Bit corresponding to Stream 0, Channel 0, BSTo0_Ch0, is transmitted on BCSTo0
and is advanced, relative to the Frame Boundary, by 10 periods of C16o, (i.e. clock period no. 2039).
The Channel Control Bit corresponding to Stream 14, Channel 0, BSTo14_Ch0, is transmitted on
BCSTo0 in advance of the Frame Boundary by three periods of output clock, C16o, (i.e. clock period
no. 2046).
Boundary by three periods of C16o, on BCSTo1.
With stream BSTo2 selected to operate at a data-rate of 2.048Mb/s, the value of the Channel Control Bit
for Channel 0 will be transmitted during the C16o clock period nos. 2040, 2048, 8, 16, 24, 32, 40 and 48.
Channel 1 will be transmitted during the C16o clock period nos. 9 and 17.
With stream BSTo4 operated at a data-rate of 8.192Mb/s, the value of the Channel Control Bit for
BORS Set LOW.
Similarly, the Channel Control Bit for BSTo15_Ch0 is advanced relative to the Frame
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