MT90871 Zarlink Semiconductor, MT90871 Datasheet - Page 29

• Manufacturer Part Number: MT90871
• Description: Flexible 8K Digital Switch (F8KDX)
• Manufacturer: Zarlink Semiconductor

Data Sheet
10.0
As operation of the memory BIST will corrupt existing data, this test must only be instigated when the device is
placed “out-of-service” or isolated from live traffic.
The memory BIST mode is enabled through the microprocessor port (section 13.13 "Memory BIST Register").
Internal BIST memory controllers generate the memory test pattern (S-march) and control the memory test.
The memory test result is monitored through the Memory BIST Register when controlled via the
microprocessor interface.
11.0
The MT90871 JTAG interface conforms to the Boundary-Scan IEEE 1149.1 standard. The operation of the
boundary-scan circuit shall be controlled by an external Test Access Port (TAP) Controller. The JTAG is
intended to be used during the development cycle. The JTAG interface is operational when the MT90871 Core
(V
11.1
The Test Access Port (TAP) consists of four input pins and one output pin described as follows:
•
•
•
•
DD_CORE
Test Clock Input (TCK)
TCK provides the clock for the TAP Controller and is independent of any on-chip clock. TCK permits the
shifting of test data into or out of the Boundary-Scan Registers cells, under the control of the TAP
Controller in Boundary-Scan Mode.
Test Mode Select Input (TMS)
The TAP controller uses the logic signals applied to the TMS input to control test operations. The TMS
signals are sampled at the rising edge of the TCK pulse. This pin is internally pulled to V
driven from an external source.
Test Data Input (TDi)
Depending on the previously applied data to the TMS input, the serial input data applied to the TDi port is
connected either to the Instruction Register or to a Test Data Register. Both registers are described in a
11.2 "TAP Registers". The applied input data is sampled at the rising edge of TCK pulses. This pin is
internally pulled to V
Test Data Output (TDo)
Depending on the previously applied sequence to the TMS input, the contents of either the instruction
) is powered at typical voltage levels.
Memory Built-In-Self-Test (BIST) Mode
JTAG Port
Test Access Port (TAP)
stream
FP
Start Ch=254
Length=4
Start Ch=0
Length=3
Start Ch=0
Length=256
FP8i
Channels containing PRBS sequence
DD_IO
Once Started BER transmission continues until stopped by the BER control register.
frame boundary
Figure 16 - Examples of BER transmission channels
0
0
0
when not driven from an external source.
1
1
1
Note: Length = Start Chan. + No. of Consecutive channels
2
2
2
3
3
3
Zarlink Semiconductor Inc.
......
......
......
.....
.....
.....
.....
.....
.....
.....
.....
.....
Channels containing data (traffic)
254
254
254
255
255
255
0
0
0
1
1
1
2
2
2
DD_IO
when not
29