BR24L16 Rohm, BR24L16 Datasheet - Page 13

• Manufacturer Part Number: BR24L16
• Description: 2k8 bit electrically erasable PROM
• Manufacturer: Rohm

Memory ICs
1) WP effective timing
Application
WP is fixed to “H” or “L” usually. But in case of controlling WP to cancel the write command, please pay attention to
During write command input, write command is canceled by controlling WP “H” within the WP cancellation effective
period.
The period from the start condition to the rising edge of the clock which take in D0 of the data (the first byte of the data
for Page Write) is the cancellation invalid period. WP input is don’t care during the period. Setup time for rising edge of
the SCL which takes in D0 must be more than 100ns.
The period from the rising edge of SCL which takes in D0 to the end of internal write cycle (t
effective period. In case of setting WP to “H” during t
accessing address is not guaranteed, so that write correct data again please.
It is not necessary waiting t
SDA
WP
WP effective timing as follows.
S
T
A
R
T
ADDRESS
SLAVE
SCL
SDA
A
C
K
L
WP cancellation invalid period
· The rising edge of the clock
which take in D0
ADDRESS
WORD
AN ENLARGEMENT
WR
D1
(5msmax.) after stopping command by WP, because the device is stand by state.
C
A
K
L
D7
D0
BR24L16-W / BR24L16F-W / BR24L16FJ-W /
D6
ACK
D5
Fig.13 WP EFFECTIVE TIMING
D4
D3
WR
D2
, WRITE operation is stopped in the middle and the data of
D1
BR24L16FV-W / BR24L16FVM-W
D0
WP cancellation effective period
A
C
K
L
No data will be written
DATA
SCL
SDA
A
C
K
L
A
C
K
L
D0
AN ENLARGEMENT
O
S
T
P
WR
ACK
) is the cancellation
Stop of the write
guaranteed
· The rising edge
Data is not
operation
of SDA
tWR
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