SSTUH32865 Philips Semiconductors, SSTUH32865 Datasheet
SSTUH32865
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SSTUH32865 Summary of contents
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... DDR2 RDIMM applications Rev. 01 — 11 March 2005 1. General description The SSTUH32865 is a 1.8 V 28-bit high output drive 1:2 register specifically designed for use on two rank by four (2R memory modules similar in function to the JEDEC-standard 14-bit DDR2 register, but integrates the functionality of the normally required two registers in a single package, thereby freeing up board real-estate and facilitating routing to accommodate high-density Dual In-line Memory Module (DIMM) designs ...
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... DDR2 Registered DIMMs (RDIMM) desiring parity checking functionality Stacked or planar high-DRAM count registered DIMMs 4. Ordering information Table 1: Ordering information Type number Solder process SSTUH32865ET/G Pb-free (SnAgCu solder ball compound) SSTUH32865ET SnPb solder ball compound 9397 750 14136 Product data sheet 1.8 V high output drive DDR registered buffer with parity 13 mm, 0 ...
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... Functional diagram VREF PARIN D0 D21 DCS0 CSGATEEN DCS1 DCKE0, 2 DCKE1 DODT0, 2 DODT1 RESET CK CK Fig 1. Functional diagram of SSTUH32865 9397 750 14136 Product data sheet 1.8 V high output drive DDR registered buffer with parity (CS ACTIVE) PARITY D Q GENERATOR AND 22 R CHECKER ...
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... V high output drive DDR registered buffer with parity SSTUH32865ET/G SSTUH32865ET ball A1 index area 002aab112 Transparent top view Rev. 01 — 11 March 2005 SSTUH32865 11 © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... GND GND VDDL VDDL GND VDDL VDDL VDDR GND VDDL VDDL GND PTYERR m.c.h. Q3B Q12B n.c. m.c.h. Q3A Q12A Rev. 01 — 11 March 2005 SSTUH32865 Q21A Q19A Q18A Q17B Q21B Q19B Q18B QODT0B QODT1B GND GND Q20B GND GND Q16B VDDR VDDR ...
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... Chip Select input is LOW during the rising edge of the clock. When LOW, the D0 to D21 inputs will be latched and redriven on every rising edge of the clock. Rev. 01 — 11 March 2005 SSTUH32865 © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... Input reference voltage for the SSTL_18 inputs. Two pins nominal (internally tied together) are used for increased reliability. power supply voltage power supply voltage ground ball present but not connected to die Rev. 01 — 11 March 2005 SSTUH32865 © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... floating floating floating Inputs floating X or floating Rev. 01 — 11 March 2005 SSTUH32865 Outputs Dn, DODTn, Qn QCS0 QCS1 DCKEn ...
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... LVCMOS. All outputs are 1.8 V CMOS drivers that have been optimized to drive the DDR2 DIMM load. The SSTUH32865 operates from a differential clock (CK and CK). Data are registered at the crossing of CK going HIGH, and CK going LOW. The device supports low-power standby operation. When the reset input (RESET) is LOW, the differential input receivers are disabled, and undriven (fl ...
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... LOW quickly except the PTYERR output, which will be floated (and will normally default HIGH by their external pull-up). 7.3.4 Power-up sequence The reset function for the SSTUH32865 is similar to that of the SSTU32864 except that the PTYERR signal is also cleared and will be held clear (HIGH) for three consecutive clock cycles. ...
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... V high output drive DDR registered buffer with parity PDM PDMSS PHL CK to PTYERR HIGH or LOW Rev. 01 — 11 March 2005 SSTUH32865 PHL PLH CK to PTYERR 002aaa983 © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... V high output drive DDR registered buffer with parity PDMSS Output signal is dependent on the prior unknown event Rev. 01 — 11 March 2005 SSTUH32865 PHL PLH CK to PTYERR HIGH or LOW © Koninklijke Philips Electronics N.V. 2005. All rights reserved. 4 002aaa984 ...
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... Product data sheet 1.8 V high output drive DDR registered buffer with parity t INACT t RPHL RESET RPLH RESET to PTYERR HIGH, LOW, or Don't care . INACT(max) Rev. 01 — 11 March 2005 SSTUH32865 002aaa985 HIGH or LOW © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... Product data sheet 1.8 V high output drive DDR registered buffer with parity Section 7 “Functional description” Rev. 01 — 11 March 2005 SSTUH32865 LATCHING AND (1) RESET FUNCTION 002aaa417 and Figure 4 “RESET © Koninklijke Philips Electronics N.V. 2005. All rights reserved. QnA ...
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... REF 0 [1] data inputs (Dn 250 mV REF [1] data inputs (Dn) - [1] data inputs (Dn 125 mV REF [1] data inputs (Dn) - [2] RESET 0.65 V [2] RESET - CK, CK 0.675 CK, CK 600 - - 0 Rev. 01 — 11 March 2005 SSTUH32865 Min Max 0.5 +2.5 [2] 0.5 +2.5 [ 100 65 +150 2 - 200 - Typ Max - 1.9 0.50 V 0.51 ...
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... mA 1 250 mV 1 REF 0 600 mV; ICR 1 GND 1 Rev. 01 — 11 March 2005 SSTUH32865 Min Typ Max Unit 1 0 100 ...
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... PARIN after CK and CK after RESET is taken HIGH. ACT(max) INACT(max) Conditions CK and CK to output CK and CK to PTYERR CK and CK to PTYERR from RESET to PTYERR [1] [2] CK and CK to output RESET to output Conditions Rev. 01 — 11 March 2005 SSTUH32865 Min Typ Max Unit - - 450 MHz ...
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... V DD input V ICR V = 600 250 mV (AC voltage levels) for differential inputs REF 250 mV (AC voltage levels) for differential inputs REF Rev. 01 — 11 March 2005 SSTUH32865 DUT T = 350 ps OUT ( ACT 90 % ...
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... PLH PHL 250 mV (AC voltage levels) for differential inputs REF 250 mV (AC voltage levels) for differential inputs REF Rev. 01 — 11 March 2005 SSTUH32865 V V ICR REF V IL 002aaa374 = V for LVCMOS inputs. ...
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... V high output drive DDR registered buffer with parity 0 input slew rate = 1 V/ns 0 DUT OUT includes probe and jig capacitance. L output dv_f DUT OUT includes probe and jig capacitance. L dv_r output Rev. 01 — 11 March 2005 SSTUH32865 20 %, unless otherwise specified test point ( 002aab117 ...
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... L LVCMOS RESET PLH output waveform 2 RESET input timing V ICR inputs t HL output waveform 1 to clock inputs Rev. 01 — 11 March 2005 SSTUH32865 20 %, unless otherwise specified test point ( 002aaa500 0. ...
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... Product data sheet 1.8 V high output drive DDR registered buffer with parity timing V ICR inputs t LH output waveform 2 clock inputs Rev. 01 — 11 March 2005 SSTUH32865 V V i(p-p) ICR 002aaa503 © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... 9.1 13.1 0.65 7.15 11.05 0.15 8.9 12.9 REFERENCES JEDEC JEITA - - - - - - Rev. 01 — 11 March 2005 SSTUH32865 detail scale 0.08 0.1 0.1 EUROPEAN PROJECTION © Koninklijke Philips Electronics N.V. 2005. All rights reserved. SOT802 ISSUE DATE 03-01- ...
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... Product data sheet 1.8 V high output drive DDR registered buffer with parity 2 called small/thin packages. Rev. 01 — 11 March 2005 SSTUH32865 3 350 mm so called © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... LBGA, LFBGA, SQFP, [3] , TFBGA, VFBGA, XSON , SO, SOJ [8] [9] [8] , PMFP , WQCCN.. measured in the atmosphere of the reflow oven. The package Rev. 01 — 11 March 2005 SSTUH32865 Soldering method Wave Reflow not suitable suitable [4] not suitable suitable suitable suitable [5] [6] not recommended suitable ...
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... Product data sheet 1.8 V high output drive DDR registered buffer with parity Data sheet status Change notice Product data sheet - Rev. 01 — 11 March 2005 SSTUH32865 Doc. number Supersedes 9397 750 14136 - © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... Rev. 01 — 11 March 2005 SSTUH32865 © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Published in The Netherlands SSTUH32865 Date of release: 11 March 2005 Document number: 9397 750 14136 ...