SSTU32866EC-S NXP Semiconductors, SSTU32866EC-S Datasheet

SSTU32866EC-S

Manufacturer Part Number
SSTU32866EC-S
Description
Manufacturer
NXP Semiconductors
Datasheet

Specifications of SSTU32866EC-S

Logic Family
SSTU
Logical Function
Registered Buffer
Number Of Elements
1
Number Of Bits
25
Number Of Inputs
25
Number Of Outputs
25
High Level Output Current
-8mA
Low Level Output Current
8mA
Package Type
LFBGA
Propagation Delay Time
3ns
Operating Supply Voltage (typ)
1.8V
Operating Supply Voltage (max)
1.9V
Operating Supply Voltage (min)
1.7V
Clock-edge Trigger Type
Posit/Negat-Edge
Polarity
Non-Inverting
Technology
CMOS
Frequency (max)
450(Min)MHz
Mounting
Surface Mount
Pin Count
96
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Not Compliant
1. General description
2. Features
The SSTU32866 is a 1.8 V configurable register specifically designed for use on DDR2
memory modules requiring a parity checking function. It is defined in accordance with the
JEDEC JESD82-7 standard for the SSTU32864 registered buffer, while adding the parity
checking function in a compatible pinout. The JEDEC standard for SSTU32866 is pending
publication. The register is configurable (using configuration pins C0 and C1) to two
topologies: 25-bit 1:1 or 14-bit 1:2, and in the latter configuration can be designated as
Register A or Register B on the DIMM.
The SSTU32866 accepts a parity bit from the memory controller on its parity bit (PAR_IN)
input, compares it with the data received on the DIMM-independent D-inputs and
indicates whether a parity error has occurred on its open-drain QERR pin (active-LOW).
The convention is even parity, that is, valid parity is defined as an even number of ones
across the DIMM-independent data inputs combined with the parity input bit.
The SSTU32866 is packaged in a 96-ball, 6
(13.5 mm by 5.5 mm).
SSTU32866
1.8 V 25-bit 1:1 or 14-bit 1:2 configurable registered buffer
with parity for DDR2 RDIMM applications
Rev. 02 — 11 November 2004
Configurable register supporting DDR2 Registered DIMM applications
Configurable to 25-bit 1:1 mode or 14-bit 1:2 mode
Controlled output impedance drivers enable optimal signal integrity and speed
Exceeds JESD82-7 speed performance (1.8 ns max. single-bit switching propagation
delay; 2.0 ns max. mass-switching)
Supports up to 450 MHz clock frequency of operation
Optimized pinout for high-density DDR2 module design
Chip-selects minimize power consumption by gating data outputs from changing state
Supports SSTL_18 data inputs
Checks parity on the DIMM-independent data inputs
Partial parity output and input allows cascading of two SSTU32866s for correct parity
error processing
Differential clock (CK and CK) inputs
Supports LVCMOS switching levels on the control and RESET inputs
Single 1.8 V supply operation
Available in 96-ball, 13.5
5.5 mm, 0.8 mm ball pitch LFBGA package
16 grid, 0.8 mm ball pitch LFBGA package
Product data sheet

Related parts for SSTU32866EC-S

SSTU32866EC-S Summary of contents

Page 1

SSTU32866 1.8 V 25-bit 1:1 or 14-bit 1:2 configurable registered buffer with parity for DDR2 RDIMM applications Rev. 02 — 11 November 2004 1. General description The SSTU32866 is a 1.8 V configurable register specifically designed for use on DDR2 ...

Page 2

... DDR2 registered DIMMs desiring parity checking functionality 4. Ordering information Table 1: Ordering information +70 C. amb Type number Solder process SSTU32866EC/G Pb-free (SnAgCu solder ball compound) SSTU32866EC SnPb solder ball compound 9397 750 14181 Product data sheet 1.8 V DDR2 configurable registered buffer with parity Package ...

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Philips Semiconductors 5. Functional diagram (1) Disabled in 1:1 configuration. Fig 1. Functional diagram of SSTU32866; 1:2 Register A configuration with and 9397 750 14181 Product data sheet 1.8 V DDR2 configurable registered buffer with parity RESET ...

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Philips Semiconductors RESET CK CK D2, D3, D5, D6 D14 V REF C1 PAR_IN C0 Fig 2. Parity logic diagram for 1:2 Register A configuration (positive logic 9397 750 14181 Product ...

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... Philips Semiconductors 6. Pinning information 6.1 Pinning Fig 3. Pin configuration for LFBGA96 Fig 4. Ball mapping, 1:1 register ( 9397 750 14181 Product data sheet 1.8 V DDR2 configurable registered buffer with parity SSTU32866EC/G ball A1 SSTU32866EC index area 002aab135 Transparent top view DCKE ...

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Philips Semiconductors Fig 5. Ball mapping, 1:2 Register A ( Fig 6. Ball mapping, 1:2 Register B ( 9397 750 14181 Product data sheet 1.8 V DDR2 configurable registered buffer ...

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Philips Semiconductors 6.2 Pin description Table 2: Symbol GND REF RESET CSR DCS D1 to D25 DODT DCKE PAR_IN Q1 to Q25, Q2A to Q14A, Q1B to Q14B PPO QCS, QCSA, QCSB QODT, ...

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Philips Semiconductors Table 2: Symbol QERR n.c. d.n.u. [1] Depends on configuration. Refer to [2] Data inputs = D2, D3, D5, D6 D25 when and Data inputs = D2, D3, D5, D6, ...

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Philips Semiconductors cascaded to the PAR_IN of the second register. The QERR output of the first register is left floating and the valid error information is latched on the QERR output of the second register error occurs and ...

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Philips Semiconductors 7.1 Function table Table 3: Function table (each flip-flop LOW voltage level HIGH voltage level don’t care; RESET DCS CSR ...

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Philips Semiconductors 8. Limiting values Table 5: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage DD V receiver input voltage I V driver output voltage O I input clamp current IK ...

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Philips Semiconductors Table 6: Recommended operating conditions Symbol Parameter V differential input voltage ID I HIGH-level output current OH I LOW-level output current OL T operating ambient temperature amb in free air [1] The RESET and Cn inputs of the ...

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Philips Semiconductors Table 8: Timing requirements At recommended operating conditions (see Symbol Parameter f clock frequency clock t pulse duration, CK, CK HIGH W or LOW t differential inputs active time ACT t differential inputs inactive time INACT t set-up ...

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Philips Semiconductors 10.1 Timing diagrams RESET DCS CSR D25 Q25 PAR_IN PPO QERR Fig 7. Timing diagram for SSTU32866 used as a single device 9397 ...

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Philips Semiconductors RESET DCS CSR D14 Q14 PAR_IN PPO QERR (not used) Fig 8. Timing diagram for the first SSTU32866 (1:2 Register A configuration) device used in pair ...

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Philips Semiconductors RESET DCS CSR D14 Q14 (1) PAR_IN PPO (not used) QERR (1) PAR_IN is driven from PPO of the first SSTU32866 device. Fig 9. Timing diagram for the second ...

Page 17

Philips Semiconductors 11. Test information 11.1 Parameter measurement information for data output load circuit All input pulses are supplied by generators having the following characteristics: PRR 10 MHz; Z The outputs are measured one at ...

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Philips Semiconductors Fig 13. Voltage waveforms; set-up and hold times Fig 14. Voltage waveforms; propagation delay times (clock to output) Fig 15. Voltage waveforms; propagation delay times (reset to output) 9397 750 14181 Product data sheet 1.8 V DDR2 configurable ...

Page 19

Philips Semiconductors 11.2 Data output slew rate measurement information All input pulses are supplied by generators having the following characteristics: PRR 10 MHz; Z (1) C Fig 16. Load circuit, HIGH-to-LOW slew measurement Fig 17. ...

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Philips Semiconductors 11.3 Error output load circuit and voltage measurement information All input pulses are supplied by generators having the following characteristics: PRR 10 MHz; Z (1) C Fig 20. Load circuit, error output measurements ...

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Philips Semiconductors Fig 23. Voltage waveforms, open-drain output LOW-to-HIGH transition time with respect to 11.4 Partial Parity Out load circuit and voltage measurement information All input pulses are supplied by generators having the following characteristics: ...

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Philips Semiconductors Fig 26. Partial Parity Out voltage waveforms; propagation delay times with respect to 9397 750 14181 Product data sheet 1.8 V DDR2 configurable registered buffer with parity LVCMOS RESET output and ...

Page 23

Philips Semiconductors 12. Package outline LFBGA96: plastic low profile fine-pitch ball grid array package; 96 balls; body 13.5 x 5.5 x 1.05 mm ball A1 index area ...

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Philips Semiconductors 13. Soldering 13.1 Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages ...

Page 25

Philips Semiconductors – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. • For packages with leads on four sides, ...

Page 26

Philips Semiconductors [4] These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, ...

Page 27

Philips Semiconductors 15. Revision history Table 13: Revision history Document ID Release date SSTU32866_2 20041111 • Modifications: The format of this data sheet has been redesigned to comply with the new presentation and information standard of Philips Semiconductors. • Data ...

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Philips Semiconductors 16. Data sheet status [1] Level Data sheet status Product status I Objective data Development II Preliminary data Qualification III Product data Production [1] Please consult the most recently issued data sheet before initiating or completing a design. ...

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Philips Semiconductors 20. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . ...

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