SSTUA32866EC/G-T NXP Semiconductors, SSTUA32866EC/G-T Datasheet
SSTUA32866EC/G-T
Specifications of SSTUA32866EC/G-T
Related parts for SSTUA32866EC/G-T
SSTUA32866EC/G-T Summary of contents
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SSTUA32866 1.8 V 25-bit 14-bit configurable registered buffer with parity for DDR2-667 RDIMM applications Rev. 02 — 26 March 2007 1. General description The SSTUA32866 is a 1.8 V configurable register specifically designed ...
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... NXP Semiconductors 4. Ordering information Table 1. Ordering information +70 C. amb Type number Solder process SSTUA32866EC/G Pb-free (SnAgCu solder ball compound) SSTUA32866EC SnPb solder ball compound 5. Functional diagram (1) Disabled configuration. Fig 1. Functional diagram of SSTUA32866 Register A configuration with and SSTUA32866_2 Product data sheet 1.8 V DDR2-667 confi ...
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... NXP Semiconductors RESET CK CK D2, D3, D5, D6 D14 VREF C1 PAR_IN C0 Fig 2. Parity logic diagram for Register A configuration (positive logic SSTUA32866_2 Product data sheet 1.8 V DDR2-667 configurable registered buffer with parity LPS0 (internal node CLK R D2, D3, D5, D6 D14 PARITY CHECK CLK ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 3. Pin configuration for LFBGA96 Fig 4. Ball mapping register ( SSTUA32866_2 Product data sheet 1.8 V DDR2-667 configurable registered buffer with parity SSTUA32866EC/G ball A1 SSTUA32866EC index area 002aab389 Transparent top view DCKE PPO VREF V DD ...
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... NXP Semiconductors Fig 5. Ball mapping Register A ( Fig 6. Ball mapping Register B ( SSTUA32866_2 Product data sheet 1.8 V DDR2-667 configurable registered buffer with parity DCKE PPO VREF DNU GND GND C D3 DNU DODT QERR GND GND n.c. GND GND G PAR_IN RESET DCS ...
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... NXP Semiconductors 6.2 Pin description Table 2. Symbol GND V DD VREF RESET CSR DCS D1 to D25 DODT DCKE PAR_IN Q1 to Q25, Q2A to Q14A, Q1B to Q14B PPO QCS, QCSA, QCSB QODT, QODTA, QODTB QCKE, QCKEA, QCKEB SSTUA32866_2 Product data sheet 1.8 V DDR2-667 configurable registered buffer with parity ...
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... NXP Semiconductors Table 2. Symbol QERR n.c. DNU [1] Depends on configuration. See [2] Data inputs = D2, D3, D5, D6 D25 when and Data inputs = D2, D3, D5, D6 D14 when and Data inputs = D10, D12, D13 when and [3] Data outputs = Q2, Q3, Q5, Q6 Q25 when and Data outputs = Q2, Q3, Q5, Q6 Q14 when and ...
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... NXP Semiconductors cascaded to the PAR_IN of the second register. The QERR output of the first register is left floating and the valid error information is latched on the QERR output of the second register error occurs and the QERR output is driven LOW, it stays latched LOW for two clock cycles or until RESET is driven LOW ...
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... NXP Semiconductors 7.1 Function table Table 3. Function table (each flip-flop LOW voltage level HIGH voltage level don’t care; RESET DCS CSR floating X or floating [ the previous state of the associated output. 0 Table 4. Parity and standby function table L = LOW voltage level HIGH voltage level don’t care; ...
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... NXP Semiconductors 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage DD V input voltage I V output voltage O I input clamping current IK I output clamping current OK I output current O I continuous current through ...
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... NXP Semiconductors 10. Characteristics Table 7. Characteristics At recommended operating conditions (see Symbol Parameter V HIGH-level output voltage OH V LOW-level output voltage OL I input current I I supply current DD I dynamic operating current DDD per MHz C input capacitance i SSTUA32866_2 Product data sheet 1.8 V DDR2-667 configurable registered buffer with parity Table 6) ...
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... NXP Semiconductors Table 8. Timing requirements At recommended operating conditions (see Symbol Parameter f clock frequency clock t pulse width W t differential inputs active time ACT t differential inputs inactive time INACT t set-up time su t hold time h [1] This parameter is not necessarily production tested. [2] VREF must be held at a valid input voltage level and data inputs must be held LOW for a minimum time of t HIGH ...
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... NXP Semiconductors 10.1 Timing diagrams RESET DCS CSR D25 Q25 PAR_IN PPO QERR Fig 7. Timing diagram for SSTUA32866 used as a single device SSTUA32866_2 Product data sheet 1.8 V DDR2-667 configurable registered buffer with parity PPO QERR Rev. 02 — 26 March 2007 SSTUA32866 ...
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... NXP Semiconductors RESET DCS CSR D14 Q14 PAR_IN PPO QERR (not used) Fig 8. Timing diagram for the first SSTUA32866 ( Register A configuration) device used in pair SSTUA32866_2 Product data sheet 1.8 V DDR2-667 configurable registered buffer with parity PPO QERR Rev. 02 — 26 March 2007 ...
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... NXP Semiconductors RESET DCS CSR D14 Q14 (1) PAR_IN PPO (not used) QERR (1) PAR_IN is driven from PPO of the first SSTUA32866 device. Fig 9. Timing diagram for the second SSTUA32866 ( Register B configuration) device used in pair SSTUA32866_2 Product data sheet 1.8 V DDR2-667 configurable registered buffer with parity ...
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... NXP Semiconductors 11. Test information 11.1 Parameter measurement information for data output load circuit All input pulses are supplied by generators having the following characteristics: PRR 10 MHz; Z The outputs are measured one at a time with one transition per measurement. CK inputs (1) C Fig 10. Load circuit, data output measurements (1) I Fig 11. Voltage and current waveforms ...
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... NXP Semiconductors Fig 13. Voltage waveforms; setup and hold times Fig 14. Voltage waveforms; propagation delay times (clock to output) Fig 15. Voltage waveforms; propagation delay times (reset to output) SSTUA32866_2 Product data sheet 1.8 V DDR2-667 configurable registered buffer with parity input V ref V = 600 ...
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... NXP Semiconductors 11.2 Data output slew rate measurement information All input pulses are supplied by generators having the following characteristics: PRR 10 MHz; Z (1) C Fig 16. Load circuit, HIGH-to-LOW slew measurement Fig 17. Voltage waveforms, HIGH-to-LOW slew rate measurement (1) C Fig 18. Load circuit, LOW-to-HIGH slew measurement Fig 19 ...
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... NXP Semiconductors 11.3 Error output load circuit and voltage measurement information All input pulses are supplied by generators having the following characteristics: PRR 10 MHz; Z (1) C Fig 20. Load circuit, error output measurements Fig 21. Voltage waveforms, open-drain output LOW-to-HIGH transition time with respect to Fig 22 ...
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... NXP Semiconductors Fig 23. Voltage waveforms, open-drain output LOW-to-HIGH transition time with respect to 11.4 Partial parity out load circuit and voltage measurement information All input pulses are supplied by generators having the following characteristics: PRR 10 MHz; Z (1) C Fig 24. Partial parity out load circuit Fig 25. Partial parity out voltage waveforms ...
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... NXP Semiconductors Fig 26. Partial parity out voltage waveforms; propagation delay times with respect to SSTUA32866_2 Product data sheet 1.8 V DDR2-667 configurable registered buffer with parity LVCMOS RESET output and t are the same PLH PHL 250 mV (AC voltage levels) for differential inputs. V ...
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... NXP Semiconductors 12. Package outline LFBGA96: plastic low profile fine-pitch ball grid array package; 96 balls; body 13.5 x 5.5 x 1.05 mm ball A1 index area ball A1 index area DIMENSIONS (mm are the original dimensions) A UNIT max. 0.41 1.2 0.51 mm 1.5 0.31 0.9 0.41 OUTLINE VERSION IEC SOT536-1 Fig 27 ...
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... NXP Semiconductors 13. Soldering This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” . 13.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...
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... NXP Semiconductors 13.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...
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... NXP Semiconductors Fig 28. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 14. Abbreviations Table 13. Acronym CMOS DDR DIMM LVCMOS PPO PRR RDIMM SSTL SSTUA32866_2 Product data sheet 1.8 V DDR2-667 confi ...
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... Document ID Release date SSTUA32866_2 20070326 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • paragraph, 2 LOW.” to “... and CK going LOW.” ...
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... For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail ...
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... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 7 Functional description . . . . . . . . . . . . . . . . . . . 7 7.1 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 9 8 Limiting values Recommended operating conditions Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 11 10.1 Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . 13 11 Test information . . . . . . . . . . . . . . . . . . . . . . . . 16 11 ...