SSTUA32866EC/G-T NXP Semiconductors, SSTUA32866EC/G-T Datasheet - Page 4

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SSTUA32866EC/G-T

Manufacturer Part Number
SSTUA32866EC/G-T
Description
Manufacturer
NXP Semiconductors
Datasheet

Specifications of SSTUA32866EC/G-T

Logic Family
SSTU
Logical Function
Registered Buffer
Number Of Elements
1
Number Of Bits
25
Number Of Inputs
25
Number Of Outputs
25
High Level Output Current
-8mA
Low Level Output Current
8mA
Propagation Delay Time
3ns
Operating Supply Voltage (typ)
1.8V
Operating Supply Voltage (max)
2V
Operating Supply Voltage (min)
1.7V
Clock-edge Trigger Type
Posit/Negat-Edge
Polarity
Non-Inverting
Technology
CMOS
Frequency (max)
450(Min)MHz
Mounting
Surface Mount
Pin Count
96
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Compliant
NXP Semiconductors
6. Pinning information
SSTUA32866_2
Product data sheet
6.1 Pinning
Fig 3. Pin configuration for LFBGA96
Fig 4. Ball mapping, 1 : 1 register (C0 = 0, C1 = 0)
M
A
B
C
D
E
G
H
K
N
P
R
F
J
L
T
Rev. 02 — 26 March 2007
PAR_IN
DCKE
DODT
D10
D11
D12
D13
D14
CK
CK
D2
D3
D5
D6
D8
D9
1
1.8 V DDR2-667 configurable registered buffer with parity
RESET
QERR
PPO
DCS
CSR
ball A1
index area
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
2
D
H
M
B
F
K
P
T
G
A
C
E
N
R
J
L
SSTUA32866EC/G
VREF
VREF
Transparent top view
GND
GND
GND
GND
GND
GND
GND
V
V
V
V
V
V
V
SSTUA32866EC
3
DD
DD
DD
DD
DD
DD
DD
1
2
3
002aab389
GND
GND
GND
GND
GND
GND
GND
V
V
V
V
V
V
V
V
V
4
4
DD
DD
DD
DD
DD
DD
DD
DD
DD
5
6
QODT
QCKE
QCS
Q10
Q11
Q12
Q13
Q14
n.c.
Q2
Q3
Q5
Q6
Q8
Q9
C1
5
002aab108
SSTUA32866
DNU
DNU
DNU
Q15
Q16
Q17
Q18
Q19
Q20
Q21
Q22
Q23
Q24
Q25
n.c.
C0
6
© NXP B.V. 2007. All rights reserved.
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