DS3105 Maxim Integrated Products, DS3105 Datasheet - Page 40

• Manufacturer Part Number: DS3105
• Description: Line Card Timing IC
• Manufacturer: Maxim Integrated Products

interrupt within the 32 ms window with appropriate action, which might include disabling external frame sync
(MCR3:EFSEN=0) to prevent the resynchronization of the 2-kHz alignment generators with SYNCn, forcing the T0
DPLL into holdover (MCR1:T0STATE=010) to avoid affecting the output clocks with any other phase hits, and
possibly even disabling the master timing card and promoting the slave timing card to master since the 2 kHz
signal from the master should not have such phase movements.
When EFSEN = 0 (external frame sync disabled) OPSTATE:FSMON is set when the negative edge of the re-
sampled SYNCn signal is outside of the window determined by FSCR3:MONLIM relative to the MFSYNC negative
edge (or positive edge if MFSYNC is inverted) and clear when within the window. When OPSTATE:FSMON is set,
the latched status bit MSR3:FSMON is also set, which can cause an interrupt if enabled in the
7.9.7 SYNCn Pins
The external frame sync signal can be automatically selected from one to three separate SYNC1,2,3 pins
depending on the setting of FSCR1:SYNCSRC[2:0] and which input clock is the T0 DPLL selected reference. If no
associated input pin is selected as the T0 DPLL input reference, the internal SYNCn signal is inactive and will not
be qualified. This function is enabled by setting FSCR3.SOURCE=11XX.
Table 7-19. External Frame Sync Source
There are three PHASEn[1:0] (n=1,2,3) select fields in the
SYNC1, PHASE2[1:0] is associated with SYNC2, and PHASE3[1:0] is associated with SYNC3. All three SYNCn
inputs can have their timing adjusted to account for frame sync signal vs. clock signal delay differences in each
path.
When this function is enabled with FSCR3.SOURCE=11XX, MCR3.AEFSEN, and MCR3.EFSEN, the monitoring
and qualification function described in Section
7.9.8 Other Configuration Options
FSYNC and MFSYNC are always produced from the T0 DPLL. The other output clocks can also be configured as 2
kHz or 8 kHz outputs, derived from the T0 DPLL.
SYNCSRC[2:0]
Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement.
XXX
0XX
1X0
1X1
Selected reference
IC3 (LVTTL)
IC4 (LVTTL)
IC5 (LVDS)
IC6 (LVDS)
IC3 or IC5
IC4 or IC6
IC9
Preliminary. Subject to Change Without Notice.
7.9.4
External Frame
Sync Source
is only performed on the selected SYNCn input pin.
40 of 110
SYNC1
SYNC2
SYNC1
SYNC2
SYNC1
SYNC2
SYNC3
FSCR2
register. PHASE1[1:0] is associated with
IER3
register.
DS3105