DS3105 Maxim Integrated Products, DS3105 Datasheet - Page 5

• Manufacturer Part Number: DS3105
• Description: Line Card Timing IC
• Manufacturer: Maxim Integrated Products

Preliminary. Subject to Change Without Notice.
DS3105
LIST OF TABLES
Table 1-1. Applicable Telecom Standards................................................................................................................... 6
Table 6-1. Input Clock Pin Descriptions .................................................................................................................... 11
Table 6-2. Output Clock Pin Descriptions.................................................................................................................. 11
Table 6-3. Global Pin Descriptions ............................................................................................................................ 12
Table 6-4. SPI Bus Mode Pin Descriptions ............................................................................................................... 13
Table 6-5. JTAG Interface Pin Descriptions .............................................................................................................. 13
Table 6-6. Power Supply Pin Descriptions ................................................................................................................ 13
Table 7-1. Input Clock Capabilities ............................................................................................................................ 17
Table 7-2. Locking Frequency Modes ....................................................................................................................... 17
Table 7-3. Default Input Clock Priorities .................................................................................................................... 20
Table 7-4. Damping Factors and Peak Jitter/Wander Gain....................................................................................... 26
Table 7-5. T0 DPLL adaptation for the T4 DPLL Phase Measurement Mode .......................................................... 30
Table 7-6. Output Clock Capabilities ......................................................................................................................... 31
Table 7-7. Digital1 Frequencies................................................................................................................................. 32
Table 7-8. Digital2 Frequencies................................................................................................................................. 33
Table 7-9. APLL Frequency to Output Frequencies (T0 APLL and T4 APLL) .......................................................... 33
Table 7-10. T0 APLL Frequency Configuration ......................................................................................................... 33
Table 7-11. T0 APLL2 Frequency Configuration ....................................................................................................... 33
Table 7-12. T4 APLL Frequency Configuration ......................................................................................................... 34
Table 7-13. OC3 and OC6 Output Frequency Selection ........................................................................................... 34
Table 7-14. Possible Frequencies for Programmable Outputs ................................................................................. 35
Table 7-15 T0CR1.T0FREQ Default Settings ........................................................................................................... 37
Table 7-16 T4CR1.T4FREQ Default Settings ........................................................................................................... 37
Table 7-17 OC6 Default Frequency Configuration .................................................................................................... 37
Table 7-18 OC3 Default Frequency Configuration .................................................................................................... 37
Table 7-19. External Frame Sync Source ................................................................................................................. 40
Table 8-1. Register Map ............................................................................................................................................ 45
Table 9-1. JTAG Instruction Codes ........................................................................................................................... 95
Table 9-2. JTAG ID Code .......................................................................................................................................... 96
Table 10-1. Recommended DC Operating Conditions .............................................................................................. 97
Table 10-2. DC Characteristics.................................................................................................................................. 97
Table 10-3. CMOS/TTL Pins ..................................................................................................................................... 98
Table 10-4. LVDS/LVPECL Input Pins ...................................................................................................................... 98
Table 10-5. LVDS Output Pins .................................................................................................................................. 98
Table 10-6. LVPECL Level-Compatible Output Pins................................................................................................. 98
Table 10-7. Input Clock Timing................................................................................................................................ 100
Table 10-8. Input Clock to Output Clock Delay ....................................................................................................... 100
Table 10-9. Output Clock Phase Alignment, Frame Sync Alignment Mode............................................................ 100
Table 10-10. SPI Interface Timing ........................................................................................................................... 101
Table 10-11. JTAG Interface Timing........................................................................................................................ 102
Table 10-12. Reset Pin Timing ................................................................................................................................ 103
Table 11-1. Pin Assignments Sorted by Signal Name............................................................................................. 104
Table 12-1. LQFP Thermal Properties, Natural Convection.................................................................................... 107
Table 12-2. LQFP Theta-JA (θ
) vs. Airflow ........................................................................................................... 107
JA
Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement.
5 of 110