DS3105 Maxim Integrated Products, DS3105 Datasheet - Page 74

• Manufacturer Part Number: DS3105
• Description: Line Card Timing IC
• Manufacturer: Maxim Integrated Products

Register Name:
Register Description:
Register Address:
Name
Default
Bits 7 to 0: Leaky Bucket ‘x’ Upper Threshold (LBxU[7:0]). See the
Register Name:
Register Description:
Register Address:
Name
Default
Bits 7 to 0: Leaky Bucket ‘x’ Lower Threshold (LBxL[7:0]). See the
Register Name:
Register Description:
Register Address:
Name
Default
Bits 7 to 0: Leaky Bucket ‘x’ Size (LBxS[7:0]). See the
Register Name:
Register Description:
Register Address:
Name
Default
Bits 1 to 0: Leaky Bucket ‘x’ Decay Rate (LBxD[1:0]). See the
Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement.
Registers LB1U, LB1L,
Registers LB2U, LB2L,
Registers LB3U, LB3L,
Registers LB1U, LB1L,
Registers LB2U, LB2L,
Registers LB3U, LB3L,
Registers LB1U, LB1L,
Registers LB2U, LB2L,
Registers LB3U, LB3L,
Registers LB1U, LB1L,
Registers LB2U, LB2L,
Registers LB3U, LB3L,
Bit 7
Bit 7
Bit 7
Bit 7
--
0
0
0
0
Bit 6
Bit 6
Bit 6
Bit 6
LB1S
LB2S
LB3S
LB1S
LB2S
LB3S
LB1S
LB2S
LB3S
LB1S
LB2S
LB3S
--
0
0
0
0
LB1U, LB2U, LB3U
Leaky Bucket 1/2/3 Upper Threshold Register
54h, 58h, 5Ch
LB1L, LB2L, LB3L
Leaky Bucket 1/2/3 Lower Threshold Register
55h, 59h, 5Dh
LB1S, LB2S, LB3S
Leaky Bucket 1/2/3 Size Register
56h, 5Ah, 5Eh
LB1D, LB2D, LB3D
Leaky Bucket 1/2/3 Decay Rate Register
57h, 5Bh, 5Fh
Preliminary. Subject to Change Without Notice.
and
and
and
and
and
and
and
and
and
and
and
and
LB1D
LB2D
LB3D
LB1D
LB2D
LB3D
LB1D
LB2D
LB3D
LB1D
LB2D
LB3D
Bit 5
Bit 5
Bit 5
Bit 5
--
0
0
0
0
together specify leaky bucket configuration 1.
together specify leaky bucket configuration 2.
together specify leaky bucket configuration 3.
together specify leaky bucket configuration 1.
together specify leaky bucket configuration 2.
together specify leaky bucket configuration 3.
together specify leaky bucket configuration 1.
together specify leaky bucket configuration 2.
together specify leaky bucket configuration 3.
together configure leaky bucket algorithm 1.
together configure leaky bucket algorithm 2.
together configure leaky bucket algorithm 3.
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Bit 4
Bit 4
Bit 4
Bit 4
--
0
0
0
0
LB0S
LBxU[7:0]
LBxS[7:0]
LBxL[7:0]
register description.
LB0D
Bit 3
Bit 3
Bit 3
Bit 3
--
0
0
1
0
LB0L
LB0U
register description.
register description.
register description.
Bit 2
Bit 2
Bit 2
Bit 2
--
1
1
0
0
Bit 1
Bit 1
Bit 1
Bit 1
1
0
0
0
LBxD[1:0]
Bit 0
Bit 0
Bit 0
Bit 0
DS3105
0
0
0
1