DS3105 Maxim Integrated Products, DS3105 Datasheet - Page 51

• Manufacturer Part Number: DS3105
• Description: Line Card Timing IC
• Manufacturer: Maxim Integrated Products

Register Name:
Register Description:
Register Address:
Name
Default
Bit 7: Frame Sync Input Monitor Alarm (FSMON). This latched status bit is set to 1 when OPSTATE:FSMON
transitions from 0 to 1. FSMON is cleared when written with a 1. When FSMON is set it can cause an interrupt
request on the INTREQ pin if the FSMON interrupt enable bit is set in the
Bit 6: T4 DPLL Lock Status Change (T4LOCK). This latched status bit is set to 1 when the lock status of the T4
DPLL (OPSTATE:T4LOCK) changes (becomes locked when previously unlocked or becomes unlocked when
previously locked). T4LOCK is cleared when written with a 1 and not set again until the T4 lock status changes
again. When T4LOCK is set it can cause an interrupt request on the INTREQ pin if the T4LOCK interrupt enable bit
is set in the
Register Name:
Register Description:
Register Address:
Name
Default
Bit 7: Frame Sync Input Monitor Alarm (FSMON). This real-time status bit indicates the current status of the
frame sync input monitor. See section 7.9.6.
Bit 6: T4 DPLL Lock Status (T4LOCK). This real-time status bit indicates the current phase lock status of the T4
DPLL. See sections
Bit 5: T0 DPLL Frequency Soft Alarm (T0SOFT). This real-time status bit indicates whether or not the T0 DPLL is
tracking its reference within the soft alarm limits specified in the SOFT[6:0] field of the
section 7.7.6.
Bit 4: T4 DPLL Frequency Soft Alarm (T4SOFT). This real-time status bit indicates whether or not the T4 DPLL is
tracking its reference within the soft alarm limits specified in the SOFT[6:0] field of the
section 7.7.6.
Bits 2 to 0: T0 DPLL Operating State (T0STATE[2:0]). This real-time status field indicates the current state of the
T0 DPLL state machine. Values not listed below correspond to invalid (unused) states. See section 7.7.1.
Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement.
0 = no alarm
1 = alarm
0 = not locked to selected reference
1 = locked to selected reference
0 = No alarm; frequency is within the soft alarm limits
1 = Soft alarm; frequency is outside the soft alarm limits
0 = No alarm; frequency is within the soft alarm limits
1 = Soft alarm; frequency is outside the soft alarm limits
001 = Free-run
010 = Holdover
100 = Locked
101 = Pre-locked 2
110 = Pre-locked
111 = Loss-of-lock
IER3
FSMON
Bit 7
FSMON
register. See section 7.7.6.
Bit 7
0
1
7.5.3
and 7.7.6.
T4LOCK
T4LOCK
Bit 6
Bit 6
1
0
MSR3
Master Status Register 3
08h
OPSTATE
Operating State Register
09h
Preliminary. Subject to Change Without Notice.
T0SOFT
Bit 5
Bit 5
--
0
0
T4SOFT
51 of 110
Bit 4
Bit 4
--
1
0
Bit 3
Bit 3
--
--
0
0
IER3
register. See section 7.9.
Bit 2
Bit 2
--
0
0
T0STATE[2:0]
DLIMIT3
DLIMIT3
Bit 1
Bit 1
--
0
0
register. See
register. See
Bit 0
Bit 0
DS3105
--
0
1