ISL6420B Intersil Corporation, ISL6420B Datasheet - Page 12

• Manufacturer Part Number: ISL6420B
• Description: Advanced Single Synchronous Buck Pulse-Width Modulation (PWM) Controller
• Manufacturer: Intersil Corporation

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Overcurrent Protection
The overcurrent function protects the converter from a shorted
output by using the upper MOSFET’s ON-resistance, r
to monitor the current. This method enhances the converter’s
efficiency and reduces cost by eliminating a current sensing
resistor.
The overcurrent function cycles the soft-start function in a
hiccup mode to provide fault protection. A resistor connected
to the drain of the upper FET and the OCSET pin programs
the overcurrent trip level. The PHASE node voltage will be
compared against the voltage on the OCSET pin, while the
upper FET is on. A current (100µA typically) is pulled from the
OCSET pin to establish the OCSET voltage. If PHASE is
lower than OCSET while the upper FET is on then an
overcurrent condition is detected for that clock cycle. The
upper gate pulse is immediately terminated, and a counter is
incremented. If an overcurrent condition is detected for
8 consecutive clock cycles, and the circuit is not in soft-start,
the ISL6420B enters into the soft-start hiccup mode. During
hiccup, the external capacitor on the ENSS pin is discharged.
After the capacitor is discharged, it is released and a soft-start
cycle is initiated. There are three dummy soft-start delay
cycles to allow the MOSFETs to cool down, to keep the
average power dissipation in hiccup mode at an acceptable
level. At the fourth soft-start cycle, the output starts a normal
soft-start cycle, and the output tries to ramp.
VOUT
PHASE
IOUT
ENSS
FIGURE 10. TYPICAL OVERCURRENT HICCUP MODE
FIGURE 9. TYPICAL SOFT-START WAVEFORM
V
IN
= 28V, V
OUT
= 3.3V, I
12
OUT
= 10A
DS(ON)
ISL6420B
During soft-start, pulse termination current limiting is
enabled, but the 8-cycle hiccup counter is held in reset until
soft-start is completed. Figure 10 shows the overcurrent
hiccup mode.
The overcurrent function will trip at a peak inductor current
(I
internal OCSET current source.
The OC trip point varies mainly due to the upper MOSFETs
r
operating load range, find the R
with:
A small ceramic capacitor should be placed in parallel with
R
presence of switching noise on the input voltage.
Voltage Margining
The ISL6420B has a voltage margining mode that can be
used for system testing. The voltage margining percentage
is resistor selectable up to ±10%. The voltage margining
mode can be enabled by connecting a margining set resistor
from VMSET pin to ground and using the control pins
GPIO1/2 to toggle between positive and negative margining
(Refer to Table 2). With voltage margining enabled, the
VMSET resistor to ground will set a current, which is
switched to the FB pin. The current will be equal to 2.468V
divided by the value of the external resistor tied to the
VMSET pin.
The power supply output increases when GPIO2 is HIGH
and decreases when GPIO1 is HIGH. The amount that the
output voltage of the power supply changes with voltage
margining, will be equal to 2.468V times the ratio of the
external feedback resistor and the external resistor tied to
VMSET. Figure 11 shows the positive and negative
margining for a 3.3V output, using a 20.5kΩ feedback
resistor and using various VMSET resistor values.
I
I
Δ
DS(ON)
OC
1. The maximum r
2. Determine
VM
OC
OCSET
V
VM
temperature.
where ΔI is the output inductor ripple current.
) determined from Equation 1, where I
=
=
I
-------------------------------------------------- -
=
----------------------- -
R
OCSET
2.468V
variations. To avoid overcurrent tripping in the normal
VMSET
2.468V
to smooth the voltage across R
r
DS ON
•
I
(
OC
R
----------------------- -
R
OCSET
VMSET
R
)
for I
DS(ON)
FB
OC
>
at the highest junction
I
OUT MAX
OCSET
(
resistor from Equation 1
)
+
(
OCSET
ΔI
OCSET
) 2 ⁄
,
in the
is the
April 27, 2009
FN6901.0
(EQ. 1)
(EQ. 2)
(EQ. 3)