PUMA2E4001-12E Mosaic Semiconductor, PUMA2E4001-12E Datasheet - Page 8

• Manufacturer Part Number: PUMA2E4001-12E
• Description: 128K x 32 EEPROM Module
• Manufacturer: Mosaic Semiconductor

ISSUE 4.2 : November 1998
The following description deals with the device, with the references to WE meaning WE1~4 on the 'A' parts.
The device read operations are initiated by both Output Enable and Chip Select LOW. The read operation is
terminated by either Chip Select or Output Enable returning HIGH. This 2-line control architecture elimanates bus
contention in a system environment. The data bus will be in a high impendence state when either Output Enable
or Chip Select is HIGH.
Write operations are initated when both Chip Select and Write Enable are LOW and Output Enable is HIGH. The
device supports both a Chip Select and Write Enable controlled write cycle. That is, the address is latched by the
falling edge of either Chip Select or Write Enable, whichever occurs last. Similarly, the data is latched internally
by the rising edge of either Chip Select or Write Enable, whichever occurs first. A byte write operation, once initiated,
will automatically continue to completion, typically within 5 ms.
The page write feature of the device allows the entire memory to be written in 5 seconds. Page Write allows 128
bytes of data to be written prior to the internal programming cycle. The host can fetch data from another location
within the system during a page write operation (change the source address), but the page address (A8 through
A16) for each subsequent valid write cycle to the part during this operation must be the same as the initial page
address.
The page write mode can be initiated during any write operation. Following the initial byte write cycle, the host can
write up to 128 bytes in the same manner as the first byte written. Each successive byte load cycle, started by the
Write Enable HIGH to LOW transition, must begin within 150 µs of the falling edge of the preceding Write Enable.
If a subsequent Write Enable HIGH to LOW transition is not detected within 150 µs, the internal automatic
programming cycle will commence.
The device features DATA Polling to indicate if the write cycle is completed. During the internal programming cycle,
any attempt to read the last byte written will produce the compliment of that data on D7. Once the programming
is complete, D7 will refect the true data. Note: If the the device is in a protected state and an illegal write operation
is attempted DATA Polling will not operate.
In addition to DATA polling, another method is provided to determine the end of a Write Cycle. During a write
operation successive attempts to read data will result in D6 toggling between 1 and 0. Once a write is complete,
this toggling will stop and valid data will be read.
The device provides three harware features to protect nonvololitile data from inadvertent writes.
Device Operation
Read
Write
DATA Polling
Hardware Data Protection
Page Mode Write
TOGGLE bit
•
•
•
inadvertent write cycle during power on or power off, maintaining data integrity.
Noise Protection - A Write Enable pulse less than 15 ns will not inditiate a write cycle.
Default V
Write Inhibit - Holding either Output Enable LOW, Write Enable HIGH or Chip Select HIGH will prevent an
CC
Sence - All functions are inhabited when V
8
CC
< 3.6 V.
PUMA 2/67/77E4001/A - 12/15/20