RC28F640P33B85 Numonyx, RC28F640P33B85 Datasheet - Page 49

• Manufacturer Part Number: RC28F640P33B85
• Description: Numonyx? Strataflash Embedded Memory
• Manufacturer: Numonyx

Numonyx™ StrataFlash
Table 25: Status Register Description (Sheet 2 of 2)
Note:
11.1.0.1
Table 26: Read Configuration Register Description (Sheet 1 of 2)
November 2007
Order Number: 314749-05
Status Register (SR)
Read Configuration Register (RCR)
15
14
13:11
Mode
Read
RM
15
Bit
2
1
0
Read Mode (RM)
Reserved (R)
Latency Count (LC[2:0])
RES
14
R
Program Suspend Status (PSS)
Always clear the Status Register prior to resuming erase operations. It avoids Status
Register ambiguity when issuing commands during Erase Suspend. If a command
sequence error occurs during an erase-suspend state, the Status Register contains the
command sequence error status (SR[7,5,4] set). When the erase operation resumes
and finishes, possible errors during the erase operation cannot be detected via the
Status Register because it contains the previous error status.
Clear Status Register
The Clear Status Register command clears the status register. It functions independent
of V
them. The Status Register should be cleared before starting a command sequence to
avoid any ambiguity. A device reset also clears the Status Register.Read Configuration
Register
The RCR is used to select the read mode (synchronous or asynchronous), and it defines
the synchronous burst characteristics of the device. To modify RCR settings, use the
Configure Read Configuration Register command (see
Bus Cycles” on page
RCR contents can be examined using the Read Device Identifier command, and then
reading from offset 0x05 (see
The RCR is shown in
Block-Locked Status (BLS)
BEFP Write Status (BWS)
13
Latency Count
Name
PP
LC[2:0]
. The WSM sets and clears SR[7,6,2], but it sets bits SR[5:3,1] without clearing
®
12
Embedded Memory (P33)
11
0 = Synchronous burst-mode read
1 = Asynchronous page-mode read (default)
Reserved bits should be cleared (0)
010 =Code 2
011 =Code 3
100 =Code 4
101 =Code 5
110 =Code 6
111 =Code 7 (default)
(Other bit settings are reserved)
Polarity
WAIT
WP
10
44).
Table
After Buffered Enhanced Factory Programming (BEFP) data is loaded into the
buffer:
0 = BEFP complete.
1 = BEFP in-progress.
Data
Hold
26. The following sections describe each RCR bit.
DH
9
Section 11.2.3, “Read Device Identifier” on page
1 = Block locked during program or erase; operation aborted.
Delay
WAIT
WD
8
0 = Block not locked during program or erase.
Burst
Seq
BS
7
0 = Program suspend not in effect.
1 = Program suspend in effect.
Edge
CLK
CE
6
Description
RES
R
5
Section 9.6, “Device Command
RES
R
4
Burst
Wrap
BW
3
Default Value = 0x80
2
Burst Length
BL[2:0]
1
Datasheet
56).
0
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