HEF4516BP,652 NXP Semiconductors, HEF4516BP,652 Datasheet

IC BINARY COUNTER UP/DOWN 16DIP

HEF4516BP,652

Manufacturer Part Number
HEF4516BP,652
Description
IC BINARY COUNTER UP/DOWN 16DIP
Manufacturer
NXP Semiconductors
Series
4000Br
Datasheets

Specifications of HEF4516BP,652

Package / Case
16-DIP (0.300", 7.62mm)
Logic Type
Binary Counter
Direction
Up, Down
Number Of Elements
1
Number Of Bits Per Element
4
Reset
Asynchronous
Timing
Synchronous
Count Rate
18MHz
Trigger Type
Positive Edge
Voltage - Supply
4.5 V ~ 15.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Through Hole
Counter Type
Binary Counters
Logic Family
HEF4516B
Number Of Bits
4
Counting Method
Synchronous
Counting Sequence
Up/Down
Operating Supply Voltage
3 V to 15 V
Operating Temperature Range
- 40 C to + 85 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
933324320652
HEF4516BPN
HEF4516BPN
1. General description
2. Features
3. Applications
4. Ordering information
Table 1.
All types operate from
Type number
HEF4516BP
HEF4516BT
Ordering information
Package
Name
DIP16
SO16
40
The HEF4516B is an edge-triggered synchronous 4-bit binary up/down counter with a
clock input (CP), an up/down count control input (UP/DN), an active LOW count enable
input (CE), an asynchronous active HIGH parallel load input (PL), four parallel inputs
(D0 to D3), four parallel outputs (Q0 to Q3), an active LOW terminal count output (TC),
and an overriding asynchronous master reset input (MR).
Information on D0 to D3 is loaded into the counter while PL is HIGH, independent of all
other input conditions except for MR which must be LOW. When PL and CE are LOW, the
counter changes on the LOW-to-HIGH transition of CP. Input UP/DN determines the
direction of the count, counting up when HIGH and counting down when LOW. When
counting up, TC is LOW when Q0 and Q3 are HIGH and CE is LOW. When counting
down, TC is LOW when Q0 to Q3 and CE are LOW. A HIGH on MR resets the counter
(Q0 to Q3 = LOW) independent of all other input conditions.
It operates over a recommended V
(usually ground). Unused inputs must be connected to V
also suitable for use over the full industrial (−40 °C to +85 °C) temperature range.
°
C to +85
HEF4516B
Binary up/down counter
Rev. 06 — 11 December 2009
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
Operates across the full industrial temperature range −40 °C to +85 °C
Complies with JEDEC standard JESD 13-B
Industrial
Description
plastic dual in-line package; 16-leads (300 mil)
plastic small outline package; 16 leads; body width 3.9 mm
°
C.
DD
power supply range of 3 V to 15 V referenced to V
DD
, V
SS
, or another input. It is
Product data sheet
Version
SOT38-4
SOT109-1
SS

Related parts for HEF4516BP,652

HEF4516BP,652 Summary of contents

Page 1

HEF4516B Binary up/down counter Rev. 06 — 11 December 2009 1. General description The HEF4516B is an edge-triggered synchronous 4-bit binary up/down counter with a clock input (CP), an up/down count control input (UP/DN), an active LOW count enable input ...

Page 2

... NXP Semiconductors 5. Functional diagram Fig 1. Functional diagram HEF4516B_6 Product data sheet PARALLEL LOAD CIRCUITRY UP/DOWN UP/DN COUNTER Rev. 06 — 11 December 2009 HEF4516B Binary up/down counter 001aae667 © NXP B.V. 2009. All rights reserved ...

Page 3

... NXP Semiconductors UP/DN CE Fig 2. Logic diagram HEF4516B_6 Product data sheet FF1 FF2 Rev. 06 — 11 December 2009 HEF4516B Binary up/down counter FF3 FF4 001aaj798 © NXP B.V. 2009. All rights reserved ...

Page 4

... NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 3. Pin configuration 6.2 Pin description Table 2. Pin description Symbol Pin 12, 13 11, 14 UP/ HEF4516B_6 Product data sheet HEF4516B UP/ 001aae689 Description parallel load input (active HIGH) parallel input count enable input (active LOW) parallel output ground supply voltage ...

Page 5

... NXP Semiconductors 7. Functional description [1] Table 3. Function table HIGH voltage level LOW voltage level don’t care; ↑ = positive-going transition. [ UP/ count Fig 4. Timing diagram HEF4516B_6 Product data sheet UP/ Rev. 06 — 11 December 2009 HEF4516B Binary up/down counter CP MODE X parallel load X no change ↑ ...

Page 6

... NXP Semiconductors Logic equation for terminal count: • ⁄ Fig 5. State diagram 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage DD I input clamping current IK V input voltage I I output clamping current ...

Page 7

... NXP Semiconductors Table 5. Recommended operating conditions Symbol Parameter Δt/ΔV input transition rise and fall rate 10. Static characteristics Table 6. Static characteristics unless otherwise specified Symbol Parameter V HIGH-level input voltage IH V LOW-level input voltage IL HIGH-level output voltage | LOW-level output voltage OL I HIGH-level output current V ...

Page 8

... NXP Semiconductors 11. Dynamic characteristics Table 7. Dynamic characteristics ° for test circuit see SS amb Symbol Parameter Conditions t HIGH to LOW PHL propagation delay Qn LOW to HIGH PLH propagation delay HEF4516B_6 Product data sheet Figure 8; unless otherwise specified. V Extrapolation formula DD [ 118 ns + (0.55 ns/pF (0.23 ns/pF ...

Page 9

... NXP Semiconductors Table 7. Dynamic characteristics ° for test circuit see SS amb Symbol Parameter Conditions t transition time t f maximum frequency see max t pulse width CP input LOW; W minimum width; see PL input HIGH; minimum width; see MR input HIGH; minimum width; see t recovery time MR input; ...

Page 10

... NXP Semiconductors Table 8. Dynamic power dissipation P P can be calculated from the formulas shown Symbol Parameter dynamic power dissipation 12. Waveforms input input UP/DN input V SS Measurement points are given in Fig 6. Waveforms showing minimum pulse width for CP, set-up and hold times for and UP/ ...

Page 11

... NXP Semiconductors negative positive a. Input waveforms b. Test circuit Test data is given in Table 9. Definitions for test circuit: DUT = Device Under Test C = Load capacitance including jig and probe capacitance Termination resistance should be equal to output impedance Z T Fig 8. Test circuit for measuring switching times Table 9 ...

Page 12

... NXP Semiconductors 13. Package outline DIP16: plastic dual in-line package; 16 leads (300 mil pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions UNIT b max. min. max. 1.73 mm 4.2 0.51 3.2 1.30 0.068 inches 0.17 0.02 0.13 0.051 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. ...

Page 13

... NXP Semiconductors SO16: plastic small outline package; 16 leads; body width 3 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.069 0.01 0.004 0.049 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...

Page 14

... NXP Semiconductors 14. Revision history Table 10. Revision history Document ID Release date HEF4516B_6 20091211 • Modifications: Section 9 “Recommended operating conditions” HEF4516B_5 20090812 HEF4516B_4 20090312 HEF4516B_CNV_3 19950101 HEF4516B_CNV_2 19950101 HEF4516B_6 Product data sheet Data sheet status Change notice Product data sheet - Δt/ΔV values updated. ...

Page 15

... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

Page 16

... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 Functional description . . . . . . . . . . . . . . . . . . . 5 8 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12 14 Revision history ...

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