74HCT4520N,112 NXP Semiconductors, 74HCT4520N,112 Datasheet - Page 2

• Manufacturer Part Number: 74HCT4520N,112
• Description: IC DUAL 4BIT SYNC BINARY 16DIP
• Manufacturer: NXP Semiconductors
• Series: 74HCTr

Specifications of 74HCT4520N,112

• Package / Case: 16-DIP (0.300", 7.62mm)
• Logic Type: Binary Counter
• Direction: Up
• Number Of Elements: 2
• Number Of Bits Per Element: 4
• Reset: Asynchronous
• Timing: Synchronous
• Count Rate: 58MHz
• Trigger Type: Positive, Negative
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Through Hole
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 74HCT4520N; 74HCT4520N; 933670460112

Philips Semiconductors
FEATURES
GENERAL DESCRIPTION
The 74HC/HCT4520 are high-speed Si-gate CMOS
devices and are pin compatible with the “4520” of the
“4000B” series. They are specified in compliance with
JEDEC standard no. 7A.
The 74HC/HCT4520 are dual 4-bit internally synchronous
binary counters with an active HIGH clock input (nCP
and an active LOW clock input (nCP
QUICK REFERENCE DATA
GND = 0 V; T
Notes
1. C
2. For HC the condition is V
ORDERING INFORMATION
See
December 1990
SYMBOL
t
t
f
C
C
PHL
PHL
max
Output capability: standard
I
Dual 4-bit synchronous binary counter
I
PD
CC
f
f
C
V
For HCT the condition is V
i
o
“74HC/HCT/HCU/HCMOS Logic Package Information”
/ t
CC
PD
= input frequency in MHz
L
category: MSI
= output frequency in MHz
(C
PLH
= output load capacitance in pF
P
= supply voltage in V
is used to determine the dynamic power dissipation (P
L
D
= C
V
CC
amb
PD
2
= 25 C; t
PARAMETER
propagation delay nCP
propagation delay nMR to nQ
maximum clock frequency
input capacitance
power dissipation capacitance per counter
V
f
o
CC
) = sum of outputs
2
f
r
i
= t
I
I
f
= GND to V
= GND to V
= 6 ns
(C
L
1
), buffered outputs
V
CC
0
, nCP
2
CC
CC
f
o
) where:
n
1
1.5 V
to nQ
0
)
n
2
.
from all four bit positions (nQ
overriding asynchronous master reset input (nMR).
The counter advances on either the LOW-to-HIGH
transition of nCP
transition of nCP
may be used as the clock input to the counter and the other
clock input may be used as a clock enable input. A HIGH
on nMR resets the counter (nQ
independent of nCP
APPLICATIONS
D
Multistage synchronous counting
Multistage asynchronous counting
Frequency dividers
CONDITIONS
C
notes 1 and 2
in W):
L
= 15 pF; V
CC
0
1
if nCP
if nCP
= 5 V 24
0
and nCP
1
0
is HIGH or the HIGH-to-LOW
is LOW. Either nCP
13
68
3.5
29
0
HC
to nQ
1
74HC/HCT4520
0
.
TYPICAL
to nQ
Product specification
3
) and an active HIGH
24
13
64
3.5
24
3
HCT
= LOW)
0
or nCP
ns
ns
MHz
pF
pF
UNIT
1