STIR4200 SigmaTel, STIR4200 Datasheet - Page 17

• Manufacturer Part Number: STIR4200
• Description: USB / IrDA Bridge Controller
• Manufacturer: SigmaTel

3-4200-D1-2.0-0403
Sensitivity Register
Default State
Note:
Bit Number Bit Mnemonic Access
Bit Number Bit Mnemonic Access
Status Register
Default State
7-5
1-0
7-5
2-0
4
3
2
4
3
1.
6.1.4.
6.1.5.
For LA9 device revision, ID (2::0) = 1 1 1
ID(2: 0) (Note 1)
RXDSNS(2: 0)
FFEMPTY
Reserved
Reserved
FFCLR
SPWIDTH
FFDIR
Reserved
Sensitivity Register
Offset 4
Status Register
Offset 5
7
7
0
N/A
WO
N/A
RO
RO
RXDSNS(2: 0)
R/W
R/W
RO
RO
Reserved
Reserved
When set, the FIFO is in transmit mode. When cleared, the FIFO is in receive mode.
When set, clears the FIFO by resetting the pointers to the empty position. This bit
must then be cleared to enable operation of the FIFO. Failing to do so, will
prohibit operation of the FIFO. The state of the bit can not be read.
When set, indicates there is no data in the FIFO.
Reserved
0
0
6
6
samples is the number of consecutive samples of an IrDA pulse it takes the
digital detector to declare the presence of a valid IrDA pulse.
Reserved. Write as zero.
SIR transmit pulse width. When cleared, the pulse width for SIR mode
transmission is 1.6usec. When set, the pulse width is 3/16
Used to program the sensitivity of the DRS demodulator. The corresponding
Revision ID of the chip.
Table 16. Sensitivity Register
Table 17. Status Register
Value
5
1
000
001
010
011
100
101
110
111
5
Reserved
FFDIR
4
0
4
1
FFCLR
SPWIDTH
3
0
Function
Function
3
0
Illegal
Illegal
Illegal
FIR
1
2
3
4
5
USB/IrDA Bridge Controller
FFEMPTY
2
1
ID(2)
2
ID(2: 0)
ID(1)
1
th
1
Reserved
the bit rate.
STIr4200
Illegal
SIR
12
16
20
24
28
4
8
0
ID(0)
0
0
17