STA027 ST Microelectronics, STA027 Datasheet - Page 20
![no-image](/images/no-image-200.jpg)
STA027
Manufacturer Part Number
STA027
Description
SBC Codec
Manufacturer
ST Microelectronics
Datasheet
1.STA027.pdf
(44 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
5 Register description
5.3.4
5.3.5
5.3.6
20/44
PLL_SYSTEM_XDIV_50 :
Address : 0xE9 (233)
Type : RW - DEC
Software Reset : 1
Description :
This register must contain a XDIV value that enables the system PLL to generate a frequency
of 50 MHZ for the SYSCK. See table 4.
Default value at soft reset assume :
PLL_SYSTEM_MDIV_50 :
Address : 0xEA (234)
Type : RW - DEC
Software Reset : 13
Description :
This register must contain a MDIV value that enables the system PLL to generate a frequency
of 50 MHz for the SYSCK. See table 4.
Default value at soft reset assume :
PLL_SYSTEM_PEL_42_5
Address : 0xE6 (230)
Type : RW - DEC
Software Reset : 126
Description :
This register must contain a PEL value that enables the system PLL to generate a frequency of
42.5 MHz for the SYSCK.See table 4.
Default value at soft reset assume :
b7
–
b7
–
b7
–
external crystal provide a CRYCK running at 14.31818 MHz
external crystal provide a CRYCK running at 14.31818 MHz
external crystal provide a CRYCK running at 14.31818 MHz
b6
b6
b6
b5
b5
b5
CD00066274
b4
b4
b4
b3
b3
b3
b2
b2
b2
b1
b1
b1
STA027
b0
b0
b0