ACS8525T Semtech, ACS8525T Datasheet - Page 7

• Manufacturer Part Number: ACS8525T
• Description: Line Card Protection Switch for SONET/SDH Systems
• Manufacturer: Semtech

The ACS8525 is a highly integrated, single-chip solution
for “Hit-less” protection switching of SEC + Sync clock
“Groups”, from Master and Slave SETS clock cards and a
third (Stand-by) source, for Line Cards in a SONET or SDH
Network Element. The ACS8525 has fast activity monitors
on the SEC clock inputs and will implement automatic
system protection switching against failure of the
selected clock. The selection of the Master/Slave input
can be forced by a Force Fast Switch pin. The Stand-by
“Group” is selected if both the Master and Slave input
clocks fail, or, if not available, the device enters a Digital
Holdover mode.
Digital Phase Locked Loop (DPLL) and Direct Digital
Synthesis (DDS) methods are used in the device so that
the overall PLL characteristics are very stable and
consistent compared to traditional analog PLLs.
The ACS8525 has three SEC/SYNC input groups from
which it can select any group as input. It generates
independent clocks on outputs 01 and 02, with a total of
53 possible output frequencies, and generates two Sync
outputs on outputs FrSync and MFrSync: 8 kHz Frame
Synchronization (FrSync) signal and 2 kHz Multi-Frame
Synchronization (MFrSync) signal.
The device has three main operating modes (states);
Free-run, Locked, or Digital Holdover. In Free-Run mode,
the ACS8525 generates a stable, low-noise clock signal at
a frequency to the same accuracy as the external
oscillator, or it can be made more accurate via software
calibration to within ±0.02 ppm. In Locked mode, the
ACS8525 selects the most appropriate of the three input
SECs and generates a stable, low-noise clock signal
locked to the selected reference. In Digital Holdover
mode, the ACS8525 generates a stable, low-noise clock
signal, adjusted to match the frequency of the last
selected SEC.
One key architectural advantage that the ACS8525 has
over traditional solutions is in the use of DPLL technology
for precise and repeatable performance over temperature
or voltage variations and between parts. The overall PLL
bandwidth, loop damping, pull-in range and frequency
accuracy are all determined by digital parameters that
provide a consistent level of performance. An Analog PLL
(APLL) takes the signal from the DPLL output and provides
a lower jitter output. The APLL bandwidth is set four orders
of magnitude higher than the DPLL bandwidth. This
ensures that the overall system performance still
maintains the advantage of consistent behavior provided
by the digital approach.
Revision 3.01/August 2005 © Semtech Corp.
Introduction
ADVANCED COMMUNICATIONS
FINAL
Page 7
The DPLLs are clocked by the external Oscillator module
(TCXO or XO) so that the Free-run or Digital Holdover
frequency stability is only determined by the stability of
the external oscillator module. This second key advantage
confines all temperature critical components to one well
defined and pre-calibrated module, whose performance
can be chosen to match the application.
All performance parameters of the DPLLs are
programmable without the need to understand detailed
PLL equations. Bandwidth, damping factor and lock range
can all be set directly.
The ACS8525 includes an SPI compatible serial interface
port, providing access to the configuration and status
registers for device setup, external control and
monitoring. The device is primarily controlled according to
values in this Register block.
Each register (8-bit wide data field) is identified and
referred to by its two-digit hexadecimal address and
name, e.g. Reg. 7D cnfg_interrupt. The “Register Map” on
page 38 summarizes the content of all of the registers,
and each register is individually described in the
subsequent Register Tables, organized in order of
ascending Address (hexadecimal), in the “Register
Descriptions” from page 42 onwards.
An Evaluation Board and intuitive GUI-based software
package is available for this device to help designers
learn how to use the ACS8525 and rapidly configure the
device for particular applications. This has its own
documentation: “ACS8525-EVB”.
The following description refers to the Block Diagram
(Figure 1 on page 1).
Inputs
The ACS8525 SETS device has input ports for input clock
groups from three sources, typically Master, Slave and
Stand-by, where each clock group comprises one SEC and
optionally one Sync signal. This is so that when any SEC
input changeover is made, the corresponding Sync signal
changeover is also made.
TTL/CMOS and PECL/LVDS ports are provided for the
Master and Slave SEC inputs to the device. The Stand-by
SEC input and three Frame Sync/Multi-frame Sync inputs
to the device are via TTL Ports. All the TTL/CMOS parts are
3 V and 5 V compatible (with clamping if required by
connecting the VDD5V pin). Refer to the “Electrical
General Description
ACS8525 LC/P
DATASHEET
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