ACS8525T Semtech, ACS8525T Datasheet - Page 9

• Manufacturer Part Number: ACS8525T
• Description: Line Card Protection Switch for SONET/SDH Systems
• Manufacturer: Semtech

PECL/LVDS Input Port Selection
The choice of PECL or LVDS compatibility is programmed
via the cnfg_differential_inputs register. Unused PECL
differential inputs should be fixed with one input High
(VDD) and the other input Low (GND), or set in LVDS mode
and left floating, in which case one input is internally
pulled High and the other Low.
Input Locking Frequency Modes
Each input port has to be configured to receive the
expected input frequency. To achieve this, three Input
Locking Frequency modes are provided: Direct Lock,
Lock8K and DivN.
Direct Lock Mode
In Direct Lock mode, DPLL1 can lock to the selected input
at the spot frequency of the input, for example 19.44 MHz
performs the DPLL phase comparisons at 19.44 MHz.
In Lock8K and DivN modes (and for the special case of
155 MHz), an internal divider is used prior to DPLL1 to
divide the input frequency before it is used for phase
comparisons.
Direct Lock Mode 155 MHz.
The max frequency allowed for phase comparison is
77.76 MHz, so for the special case of a 155 MHz input set
to Direct Lock mode, there is a divide-by-two function
automatically selected to bring the frequency down to
within the limits of operation.
Lock8K Mode
Lock8K mode automatically sets the divider parameters
to divide the input frequency down to 8 kHz. Lock8K can
only be used on the supported spot frequencies (see
Table 4 Note(i)). Lock8k mode is enabled by setting the
Lock8k bit (Bit 6) in the appropriate
cnfg_ref_source_frequency register location. Using lower
frequencies for phase comparisons in the DPLL results in
a greater tolerance to input jitter. It is possible to choose
which edge of the input reference clock to lock to, by
setting 8K Edge Polarity (Bit 2 of Reg. 03, test_register1).
DivN Mode
In DivN mode, the divider parameters are set manually by
configuration (Bit 7 of the cnfg_ref_source_frequency
register), but must be set so that the frequency after
division is 8 kHz.
The DivN function is defined as:
Revision 3.01/August 2005 © Semtech Corp.
ADVANCED COMMUNICATIONS
FINAL
Page 9
DivN = “Divide by N + 1”, i.e. it is the dividing factor used
for the division of the input frequency, and has a value of
(N + 1) where N is an integer from 1 to 15624 inclusive.
Therefore, in DivN mode the input frequency can be
divided by any integer value between 2 to 15625.
Consequently, any input frequency which is a multiple of
8 kHz, between 8 kHz and 125 MHz, can be supported by
using DivN mode.
Note...Any reference input can be set to use DivN
independently of the frequencies and configurations of the
other inputs. However only one value of N is allowed, so all
inputs with DivN selected must be running at the same
frequency.
DivN Examples
(a) To lock to 2.000 MHz:
(b) To lock to 10.000 MHz:
Input SEC Activity Monitors
An input reference activity monitor is assigned to each of
the three SEC inputs. The monitors operate continuously
such that at all times the activity status of each SEC input
is known.
SEC activity monitoring is used to declare whether or not
an input is valid. Any SEC that suffers a loss-of-activity will
be declared as invalid and unavailable for selection.
SEC activity monitoring is a continuous process which is
used to identify clock problems. There is a difference in
(i)
(ii) To achieve 8 kHz, the 2 MHz input must be
(i)
(ii) To achieve 8 kHz, the 10 MHz input must be
Set the cnfg_ref_source_frequency register to
10XX0000 (binary) to enable DivN, and set the
frequency to 8 kHz - the frequency required after
division. (XX = “Leaky Bucket” ID for this input).
divided by 250. So, if DivN = 250 = (N + 1)
then N must be set to 249. This is done by writing
F9 hex (249 decimal) to the DivN register pair
Reg. 46/47.
The cnfg_ref_source_frequency register is set to
10XX0000 (binary) to set the DivN and the
frequency to 8 kHz, the post-division frequency.
(XX = “Leaky Bucket” ID for this input).
divided by 1,250. So, if DivN, = 250 = (N+1)
then N must be set to 1,249. This is done by
writing 4E1 hex (1,249 decimal) to the DivN
register pair Reg. 46/47.
ACS8525 LC/P
DATASHEET
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