IDT72T51546 Integrated Device Technology, IDT72T51546 Datasheet - Page 49

• Manufacturer Part Number: IDT72T51546
• Description: 2.5v Multi-queue Flow-control Devices 32 Queues 36 Bit Wide Configuration 1,179,648 Bits And 2,359,296 Bits
• Manufacturer: Integrated Device Technology

Cycle:
*A* Queue 5 of Device 1 is selected on the write port. A queue within Device 2 had previously been selected. The PAF output of device 1 is High-Impedance.
*B* No write occurs.
*C* No write occurs.
*D* Word, Wd-m is written into Q5 causing the PAF flag to go from LOW to HIGH. The flag latency is 3 WCLK cycles + t
*E* Queue 9 in device 1 is now selected for write operations. This queue is not almost full, therefore the PAF flag will update after a 3 WCLK + t
*F* The PAF flag goes LOW based on the write 2 cycles earlier.
*G* No write occurs.
*H* The PAF flag goes HIGH due to the queue switch to Q9.
NOTE:
1. The waveform here shows the PAF flag operation when no queue switches are occurring and a queue selected on both the write and read ports is being written to then read
IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
WRADD
WADEN
PAF
(Device 1)
PAF
(Device 2)
WCLK
RCLK
WCLK
from at the almost full boundary.
Flag Latencies:
Assertion: 2*WCLK + t
De-assertion: t
If t
WEN
REN
PAF
WEN
SKEW2
Din
t
is violated there will be one extra WCLK cycle.
CLKL
HIGH-Z
t
SKEW2
AS
t
QS
D
+ WCLK + t
*A*
1
Q
WAF
5
t
ENS
t
QH
t
AH
WAF
D - (m+1) words in Queue
t
CLKL
*B*
t
ENH
Figure 23. Almost Full Flag Timing and Queue Switch
*C*
1
(
2)
Figure 24. Almost Full Flag Timing
D
t
1
ENS
Q
t
DS
5
W
*D*
D-m
2
49
t
WAF
t
t
t
FFHZ
ENH
DH
t
AFLZ
t
t
AS
QS
t
ENS
D
1
*E*
Q
1
9
t
SKEW2
t
QH
t
AH
t
ENH
D - m words in Queue
*F*
WAF
2
.
t
WAF
COMMERCIAL AND INDUSTRIAL
*G*
TEMPERATURE RANGES
WAF
1
t
WAF
latency.
*H*
D-(m+1) words
in Queue
5998 drw29
t
WAF
5998 drw28