IDT72T51546 Integrated Device Technology, IDT72T51546 Datasheet - Page 58

no-image

IDT72T51546

Manufacturer Part Number
IDT72T51546
Description
2.5v Multi-queue Flow-control Devices 32 Queues 36 Bit Wide Configuration 1,179,648 Bits And 2,359,296 Bits
Manufacturer
Integrated Device Technology
Datasheet
NOTES:
1. If devices are configured for Direct operation of the PAFn/PAEn flag busses the FXI/EXI of the MASTER device should be tied LOW. All other devices tied HIGH. The FXO/EXO
2. Q outputs must not be mixed between devices, i.e. Q0 of device 1 must connect to Q0 of device 2, etc.
IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
Serial Programming Data Input
Serial Enable
Data Bus
Write Clock
Write Queue Select
Write Address
Full Strobe
Programmable Almost Full
Full Sync1
Full Flag
Almost Full Flag
Serial Clock
Write Enable
Full Sync n
outputs are DNC (Do Not Connect).
Full Sync2
DONE
Figure 35. Multi-Queue Expansion Diagram
WADEN
D 0 -D 35
D 0 -D 35
WCLK
WEN
FSTR
PAFn
FSYNC
FF
PAF
SCLK
D 0 -D 35
WCLK
WEN
WRADD
FSTR
PAFn
FSYNC
FF
PAF
WCLK
WEN
WRADD
WADEN
FSTR
PAFn
FSYNC
FF
PAF
SCLK
WRADD
WADEN
SCLK
SENI
SENO
SENO
SENI
SENO
SENI
SI
DEVICE
SO FXO EXO
SI
DEVICE
FXO EXO
SO FXO EXO
FXI
SI
DEVICE
1
n
FXI
FXI
2
58
EXI
EXI
EXI
Q 0 -Q 35
RADEN
Q 0 -Q 35
Q 0 -Q 35
RADEN
RADEN
RDADD
ESYNC
ESYNC
RDADD
ESYNC
RDADD
PAEn
RCLK
RCLK
ESTR
RCLK
ESTR
ESTR
PAEn
PAEn
REN
REN
PAE
REN
PAE
PAE
OV
OV
PR
PR
PR
OV
COMMERCIAL AND INDUSTRIAL
5998 drw40
TEMPERATURE RANGES
Programmable Almost Empty
Read Queue Select
Almost Empty Flag
Output Valid Flag
Output Data Bus
Read Address
Empty Sync n
Empty Strobe
Empty Sync 1
Empty Sync 2
Read Enable
Read Clock
Packet
Reads

Related parts for IDT72T51546