IDT72T51546 Integrated Device Technology, IDT72T51546 Datasheet - Page 9

• Manufacturer Part Number: IDT72T51546
• Description: 2.5v Multi-queue Flow-control Devices 32 Queues 36 Bit Wide Configuration 1,179,648 Bits And 2,359,296 Bits
• Manufacturer: Integrated Device Technology

PIN DESCRIPTIONS (CONTINUED)
IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
OE
(M14)
OV
(P9)
OW
(L16)
PAE
(P10)
PAEn/PRn
(PAE7-P11
PAE6-P12
PAE5-R12
PAE4-T12
PAE3-P13
PAE2-R13
PAE1-T13
PAE0-T14)
PAF
(R8)
PAFn
(PAF7-P7
PAF6-P6
PAF5-R6
PAF4-R7
PAF3-P5
PAF2-R5
PAF1-T5
PAF0-T4)
PD
(K1)
PKT
(J14)
Symbol &
Pin No.
(1)
(1)
Output Enable
Output Valid
Flag
Output Width
Programmable
Almost-Empty
Flag
Programmable
Almost-Empty
Flag Bus/Packet
ReadyFlag Bus
Programmable
Almost-Full Flag
Programmable
Almost-Full Flag
Power Down
Packet Mode
Bus
Name
HSTL-LVTTL The Output enable signal is an Asynchronous signal used to provide three-state control of the multi-queue
HSTL-LVTTL This output flag provides output valid status for the data word present on the multi-queue flow-control device
HSTL-LVTTL This pin provides the Almost-Empty flag status for the Queue that has been selected on the output port
HSTL-LVTTL On the 32Q device the PAEn/PRn bus is 8 bits wide. During a Master Reset this bus is setup for either
HSTL-LVTTL This pin provides the Almost-Full flag status for the Queue that has been selected on the input port for
HSTL-LVTTL On the 32Q device the PAFn bus is 8 bits wide. At any one time this output bus provides PAF status
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
I/O TYPE
INPUT
LVTTL
INPUT
INPUT
LVTTL
INPUT
HSTL
This pin is setup during Master Reset and must not toggle during any device operation. This pin is used
providing both a Packet Ready (PR) output and a Programmable Almost Empty (PAE) discrete output,
data output bus, Qout. If a device has been configured as a “Master” device, the Qout data outputs will
be in a Low Impedance condition if the OE input is LOW. If OE is HIGH then the Qout data outputs will be
in High Impedance. If a device is configured a “Slave” device, then the Qout data outputs will always be
in High Impedance until that device has been selected on the Read Port, at which point OE provides three-
state of that respective device.
data output port, Qout. This flag is therefore, 2-stage delayed to match the data output path delay. That
is, there is a 2 RCLK cycle delay from the time a given queue is selected for reads, to the time the OV
flag represents the data in that respective queue. When a selected queue on the read port is read to
empty, the OV flag will go HIGH, indicating that data on the output bus is not valid. The OV flag also has
High-Impedance capability, required when multiple devices are used and the OV flags are tied together.
in conjunction with IW and BM to setup the data input and output bus widths to be a combination of x9,
x18 or x36, (providing that one port is x36).
for read operations, (selected via RCLK, RDADD and RADEN). This pin is LOW when the selected
Queue is almost-empty. This flag output may be duplicated on one of the PAEn bus lines. This flag is
synchronized to RCLK.
Almost Empty mode or Packet mode. This output bus provides PAE/PRn status of 8 queues (1 quadrant),
within a selected device, having a total of 4 quadrants. During Queue read/write operations these outputs
provide programmable empty flag status or packet ready status, in either direct or polled mode. The mode
of flag operation is determined during master reset via the state of the FM input. This flag bus is capable of
High-Impedance state, this is important during expansion of multi-queue devices. During direct operation
the PAEn/PRn bus is updated to show the PAE/PR status of a quadrant of queues within a selected device.
Selection is made using RCLK, ESTR and RDADD. During Polled operation the PAEn/PRn bus is
loaded with the PAE/PRn status of multi-queue flow-control quadrants sequentially based on the rising
edge of RCLK. PAE or PR operation is determined by the state of PKT during master reset.
write operations, (selected via WCLK, WRADD and WADEN). This pin is LOW when the selected
Queue is almost-full. This flag output may be duplicated on one of the PAFn bus lines. This flag is
synchronized to WCLK.
of 8 queues (1 quadrant), within a selected device, having a total of 4 quadrants. During Queue read/
write operations these outputs provide programmable full flag status, in either direct or polled mode. The
mode of flag operation is determined during master reset via the state of the FM input. This flag bus is
capable of High-Impedance state, this is important during expansion of multi-queue devices. During direct
operation the PAFn bus is updated to show the PAF status of a quadrant of queues within a selected
device. Selection is made using WCLK, FSTR, WRADD and WADEN. During Polled operation the PAFn
bus is loaded with the PAF status of multi-queue flow-control quadrants sequentially based on the rising
edge of WCLK.
This input is used to provide additional power savings. When the device I/O is setup for HSTL/eHSTL
mode a HIGH on the PD input disables the data inputs on the write port only, providing significant power
savings. In LVTTL mode this pin has no operation
The state of this pin during a Master Reset will determine whether the part is operating in Packet mode
or standard mode, providing a (PAE) output only. If this pin is HIGH during Master Reset the part will
operate in packet mode, if it is LOW then almost empty mode. If packet mode has been selected the read
port flag bus becomes packet ready flag bus, PRn and the discrete packet ready flag, PR is functional.
If almost empty operation has been selected then the flag bus provides almost empty status, PAEn and
9
Description
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES