IDT72T51336 ETC-unknow, IDT72T51336 Datasheet - Page 12

• Manufacturer Part Number: IDT72T51336
• Description: 2.5v Multi-queue Flow-control Devices 8 Queues 36 Bit Wide Configuration 589,824 Bits, 1,179,648 Bits And 2,359,296 Bits
• Manufacturer: ETC-unknow

WRADD4-R1
PIN DESCRIPTIONS (CONTINUED)
NOTES:
1. Inputs should not change after Master Reset.
2. These pins are for the JTAG port. Please refer to pages 56-60 and Figures 34-36.
PIN NUMBER TABLE
IDT72T51336/72T51346/72T51356 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
WEN
(T6)
WRADD
[5:0]
(WRADD5-T1
WRADD3-R2
WRADD2-P3
WRADD1-N1
WRADD0-N2)
V
V
(See Pin No.
table below)
GND
Vref
(K3)
D[35:0]
Din
Q[35:0]
Qout
V
V
GND
Symbol
DDQ
CC (See below)
DDQ
CC
Symbol &
Pin No.
(See below)
Data Input Bus
Data Output Bus HSTL-LVTTL Q(35,34)-J(15,16), Q(33-31)-H(14-16), Q(30-28)-G(14-16), Q(27-25)-F(14-16), Q(24-22)-E(14-16),
+2.5V Supply
O/P Rail Voltage
Ground Pin
Write Enable
Write Address
Bus
+2.5V Supply
O/P Rail Voltage
Ground Pin
Reference
Voltage
Name
Name
HSTL-LVTTL D35-J3, D(34-32)-H(3-1), D(31-29)-G(3-1), D(28-26)-F(3-1), D(25-23)-E(3-1), D(22-20)-D(3-1),
OUTPUT
HSTL-LVTTL The WEN input enables write operations to a selected queue based on a rising edge of WCLK. A queue
HSTL-LVTTL For the 8Q device the WRADD bus is 6 bits. The WRADD bus is a dual purpose address bus. The first
I/O TYPE
Ground
INPUT
Power
Power
I/O TYPE
Ground
INPUT
INPUT
INPUT
Power
Power
HSTL
D(19-17)-C(3-1), D(16,15)-B(2,1), D(14-12)-A(1-3), D11-B3, D10-A4, D9-B4, D8-C4, D7-A5, D6-B5,
D5-C5, D4-A6, D3-B6, D2-C6, D1-A7, D0-B7
Q(21,20)-D(15,16), Q19-B16, Q(18,17)-C(16,15), Q16-D14, Q(15,14)-A(16,15), Q13-B15, Q12-A14,
Q11-B14, Q10-C14, Q9-A13, Q8-B13, Q7-C13, Q6-A12, Q5-B12, Q4-C12, Q3-A11, Q2-B11,
Q(1,0)-C(11,10)
D(7-10), E(6,7,10,11), F(5,12), G(4,5,12,13), H(4,13), J(4,13), K(4,5,12,13), L(5,12), M(6,7,10,11), N(7-10)
E(8,9), F(6-11), G(6-11), H(5-12), J(1,5-12), K(2,6-11,14), L(6-11), M(8,9), N(15,16), P(1,2)
D(4-6,11-13), E(4,5,12,13), F(4,13), L(4,13), M(4,5,12,13), N(4-6,11-13)
to be written to can be selected via WCLK, WADEN and the WRADD address bus regardless of the state
of WEN. Data present on Din can be written to a newly selected queue on the second WCLK cycle after
queue selection provided that WEN is LOW. A write enable is not required to cycle the PAFn bus (in
polled mode) or to select the device, (in direct mode).
function of WRADD is to select a queue to be written to. The least significant 3 bits of the bus, WRADD[2:0]
are used to address 1 of 8 possible queues within a multi-queue device. The most significant 3 bits,
mode. These 3 MSB’s will address a device with the matching ID code. The address present on the
WRADD bus will be selected on a rising edge of WCLK provided that WADEN is HIGH, (note, that data
present on the Din bus can be written into the previously selected queue on this WCLK edge and on the
next rising WCLK also, providing that WEN is LOW). Two WCLK rising edges after write queue select,
data can be written into the newly selected queue.
The second function of the WRADD bus is to select the device of queues to be loaded on to the PAFn
bus during strobed flag mode. The most significant 3 bits, WRADD[5:3] are again used to select 1 of 8
possible multi-queue devices that may be connected in expansion mode. Address bits WRADD[2:0]
are don’t care during quadrant selection. The quadrant address present on the WRADD bus will be selected
on the rising edge of WCLK provided that FSTR is HIGH, (note, that data can be written into the previously
selected queue on this WCLK edge). Please refer to Table 1 for details on the WRADD bus.
These are V
to +2.5V, for HSTL these pins must be connected to +1.5V and for eHSTL these pins must be connected
to +1.8V.
These are Ground pins and must all be connected to the GND supply rail.
This is a Voltage Reference input and must be connected to a voltage level determined from the table
"Recommended DC Operating Conditions". The input provides the reference level for HSTL/eHSTL
inputs. For LVTTL I/O mode this input should be tied to GND.
WRADD[5:3] are used to select 1 of 8 possible multi-queue devices that may be connected in expansion
These pins must be tied to the desired output rail voltage. For LVTTL I/O these pins must be connected
CC
power supply pins and must all be connected to a +2.5V supply rail.
12
Pin Number
Description
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES