IDT72T51336 ETC-unknow, IDT72T51336 Datasheet - Page 39

• Manufacturer Part Number: IDT72T51336
• Description: 2.5v Multi-queue Flow-control Devices 8 Queues 36 Bit Wide Configuration 589,824 Bits, 1,179,648 Bits And 2,359,296 Bits
• Manufacturer: ETC-unknow

Cycle:
*A* Queue 3 of Device 1 is selected for read operations. The OV is currently being driven by Device 2, a queue within device 2 is selected for reads. Device 2 also has control
*B* Reads are now enabled. A word from the previously selected queue of Device 2 will be read out.
*C* After a queue switch, there is a 3 RCLK latency for output data.
*D* The Qout of Device 1 goes to Low-Impedance and word Wd is read from Q3 of D1. This happens to be the last word of Q3. Device 2 places its Qout outputs into
*E* Queue 2 of device 1 is selected for read operations. The last word of Q3 was read on the previous cycle, therefore OV goes HIGH to indicate that the data on the Qout is
*F* The last word of Q3 remains on the Qout bus, OV is HIGH, indicating that this word has been previously read.
*G* The next word (We-1), available from the newly selected queue, Q2 of device 1 is now read out. This will occur regardless of REN, 2 RCLK cycles after queue selection
*H* The last word, We is read from Q2, this queue is now empty.
*I* The OV flag goes HIGH to indicate that Q2 was read to empty on the previous cycle.
*J* Due to a write operation the OV flag goes LOW and data word W0 is read from Q2. The latency is: t
IDT72T51336/72T51346/72T51356 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
Qout
(Device 1)
RDADD
RADEN
OV
(Device 1)
OV
(Device 2)
WRADD
WADEN
RCLK
WCLK
REN
WEN
of Qout bus, its Qout outputs are in Low-Impedance. This diagram only shows the Qout outputs of device 1. (Reads are disabled).
High-Impedance, device 1 has control of the Qout bus. The OV flag of Device 2 goes to High-Impedance and Device 1 takes control of OV. The OV flag of Device 1 goes LOW
to show that Wd of Q3 is valid.
not valid (Q3 was read to empty). Word, Wd remains on the output bus.
due to the FWFT operation. The OV flag updates 3 RCLK cycles after a queue selection.
Din
HIGH-Z
t
AS
t
QS
D
*A*
1
Q
3
t
QH
t
AH
Addr=001011
t
ENS
*B*
*C*
Figure 14. Output Valid Flag Timing (In Expansion Mode)
t
OLZ
t
t
QS
AS
*D*
D
1
t
Q
t
OVLZ
OVHZ
2
t
A
t
t
t
t
AS
QS
QH
AH
Addr=001010
D
1
*E*
Q
2
t
D
39
QH
t
AH
t
Addr=001010
1
ROV
Q
3
W
D
Last Word
*F*
SKEW1
+ 1*RCLK + t
*G*
t
A
PFT W
D
t
ENS
ROV
1
t
DS
Q
*H*
.
2
e-1
D
COMMERCIAL AND INDUSTRIAL
W
1
t
A
Q
t
0
ROV
2
t
SKEW1
t
t
ENH
DH
D
TEMPERATURE RANGES
1
*I*
Q
2
W
e
t
Last Word
ROV
*J*
t
A
t
ROV
W
6114 drw19
D
0
Q
1
2