IDT72T51336 ETC-unknow, IDT72T51336 Datasheet - Page 9

• Manufacturer Part Number: IDT72T51336
• Description: 2.5v Multi-queue Flow-control Devices 8 Queues 36 Bit Wide Configuration 589,824 Bits, 1,179,648 Bits And 2,359,296 Bits
• Manufacturer: ETC-unknow

PIN DESCRIPTIONS (CONTINUED)
IDT72T51336/72T51346/72T51356 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
OV
(P9)
OW
(L16)
PAE
(P10)
PAEn/PRn
(PAE7-P11
PAE6-P12
PAE5-R12
PAE4-T12
PAE3-P13
PAE2-R13
PAE1-T13
PAE0-T14)
PAF
(R8)
PAFn(PAF7-P7 Programmable
(PAF6-P6
PAF5-R6
PAF4-R7
PAF3-P5
PAF2-R5
PAF1-T5
PAF0-T4)
PD
(K1)
PKT
(J14)
PR
(R9)
Symbol &
(1)
Pin No.
(1)
Output Valid
Flag
Output Width
Programmable
Almost-Empty
Flag
Programmable
Almost-Empty
Flag Bus/Packet
Ready Flag Bus
Programmable
Almost-Full Flag
Almost-Full Flag
Bus
Power Down
Packet Mode
Packet Ready
Flag
Name
HSTL-LVTTL This output flag provides output valid status for the data word present on the multi-queue flow-control device
HSTL-LVTTL This pin provides the Almost-Empty flag status for the queue that has been selected on the output port
HSTL-LVTTL On the 8Q device the PAEn/PRn bus is 8 bits wide. During a Master Reset this bus is setup for either
HSTL-LVTTL This pin provides the Almost-Full flag status for the queue that has been selected on the input port for write
HSTL-LVTTL On the 8Q device the PAFn bus is 8 bits wide. At any one time this output bus provides PAF status
HSTL-LVTTL If packet mode has been selected this flag output provides Packet Ready status of the Queue selected
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
I/O TYPE
INPUT
INPUT
LVTTL
LVTTL
INPUT
HSTL
data output port, Qout. This flag is therefore, 2-stage delayed to match the data output path delay. That
is, there is a 2 RCLK cycle delay from the time a given queue is selected for reads, to the time the OV flag
represents the data in that respective queue. When a selected queue on the read port is read to empty,
the OV flag will go HIGH, indicating that data on the output bus is not valid. The OV flag also has High-
Impedance capability, required when multiple devices are used and the OV flags are tied together.
This pin is setup during Master Reset and must not toggle during any device operation. This pin is used
in conjunction with IW and BM to setup the data input and output bus widths to be a combination of x9,
x18 or x36, (providing that one port is x36).
for read operations, (selected via RCLK, RDADD and RADEN). This pin is LOW when the selected
queue is almost-empty. This flag output may be duplicated on one of the PAEn bus lines. This flag is
synchronized to RCLK.
Almost Empty mode or Packet mode. This output bus provides PAE/PRn status of all 8 queues within a
selected device. During queue read/write operations these outputs provide programmable empty flag
status or packet ready status, in either direct or polled mode. The mode of flag operation is determined
during master reset via the state of the FM input. This flag bus is capable of High-Impedance state, this
is important during expansion of multi-queue devices. During direct operation the PAEn/PRn bus is
updated to show the PAE/PR status of queues within a selected device. Selection is made using RCLK,
ESTR and RDADD. During Polled operation the PAEn/PRn bus is loaded with the PAE/PRn status of
multi-queue flow-control devices sequentially based on the rising edge of RCLK. PAE or PR operation
is determined by the state of PKT during master reset.
operations, (selected via WCLK, WRADD and WADEN). This pin is LOW when the selected queue is
almost-full. This flag output may be duplicated on one of the PAFn bus lines. This flag is synchronized to WCLK.
of all 8 queues within a selected device. During queue read/write operations these outputs provide
programmable full flag status, in either direct or polled mode. The mode of flag operation is determined
during master reset via the state of the FM input. This flag bus is capable of High-Impedance state,
this is important during expansion of multi-queue devices. During direct operation the PAFn bus is
updated to show the PAF status of a quadrant of queues within a selected device. Selection is made
using WCLK, FSTR, WRADD and WADEN. During Polled operation the PAFn bus is loaded with the
PAF status of multi-queue flow-control quadrants sequentially based on the rising edge of WCLK.
This input is used to provide additional power savings. When the device I/O is setup for HSTL/eHSTL
mode a HIGH on the PD input disables the data inputs on the write port only, providing significant power
savings. In LVTTL mode this pin has no operation
The state of this pin during a Master Reset will determine whether the part is operating in Packet mode
providing both a Packet Ready (PR) output and a Programmable Almost Empty (PAE) discrete output,
or standard mode, providing a (PAE) output only. If this pin is HIGH during Master Reset the part will
operate in packet mode, if it is LOW then almost empty mode. If packet mode has been selected the read
port flag bus becomes packet ready flag bus, PRn and the discrete packet ready flag, PR is functional.
If almost empty operation has been selected then the flag bus provides almost empty status, PAEn and
the discrete almost empty flag, PAE is functional, the PR flag is inactive and should not be connected.
Packet Ready utilizes user marked locations to identify start and end of packets being written into the
device. Packet Mode can only be selected if both the input port width and output port width are 36 bits.
for read operations. During a master reset the state of the PKT input determines whether Packet mode
of operation will be used. If Packet mode is selected, then the condition of the PR flag and OV signal are
asserted indicates a packet is ready for reading. The user must mark the start of a packet and the end of
a packet when writing data into a queue. Using these Start Of Packet (SOP) and End Of Packet (EOP)
markers, the multi-queue device sets PR LOW if one or more “complete” packets are available in the queue.
A complete packet(s) must be written before the user is allowed to switch queues.
9
Description
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES