IDT72T51336 ETC-unknow, IDT72T51336 Datasheet - Page 19

• Manufacturer Part Number: IDT72T51336
• Description: 2.5v Multi-queue Flow-control Devices 8 Queues 36 Bit Wide Configuration 589,824 Bits, 1,179,648 Bits And 2,359,296 Bits
• Manufacturer: ETC-unknow

signaled by the SENO output of a device going from HIGH to LOW. Note, that
SENI must be held LOW when a device is setup for default programming mode.
the first device in a chain can be held LOW. The SENO of a device should connect
to the SENI of the next device in the chain. The SENO of the final device is used
to indicate that default programming of all devices is complete. When the final
SENO goes LOW normal operations may begin. Again, all devices will be
programmed with their maximum number of queues and the memory divided
equally between them. Please refer to Figure 9, Default Programming.
READING AND WRITING TO THE IDT MULTI-QUEUE
FLOW-CONTROL DEVICE
can be configured in two distinct modes, namely Standard Mode and Packet
Mode.
STANDARD MODE OPERATION (PKT = LOW ON MASTER RESET)
WRITE QUEUE SELECTION AND WRITE OPERATION
(STANDARD MODE)
can be configured up to a maximum of 8 queues into which data can be written
via a common write port using the data inputs (Din), write clock (WCLK) and write
enable (WEN). The queue to be written is selected by the address present on
the write address bus (WRADD) during a rising edge on WCLK while write
address enable (WADEN) is HIGH. The state of WEN does not impact the queue
TABLE 1 — WRITE ADDRESS BUS, WRADD[5:0]
IDT72T51336/72T51346/72T51356 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
When multi-queue devices are connected in expansion mode, the SENI of
The IDT72T51336/72T51346/72T51356 multi-queue flow-control devices
The IDT72T51336/72T51346/72T51356 multi-queue flow-control devices
Write Queue
Bus Device
PAFn Flag
Operation WCLK WADEN FSTR
Select
Select
1
0
19
selection. The queue selection requires 1 WCLK cycle. All subsequent data
writes will be to this queue until another queue is selected.
device as opposed to Packet Mode where complete packets may be written.
The write port is designed such that 100% bus utilization can be obtained. This
means that data can be written into the device on every WCLK rising edge
including the cycle that a new queue is being addressed.
(see Figure 10, Write Queue Select, Write Operation and Full flag Operation).
WADEN goes high signaling a change of queue (clock cycle “A”). The address
on WRADD at that time determines the next queue. Data presented during that
cycle (“A”) and the next cycle (“B” and “C”), will be written to the active (old)
queue, provided WEN is active LOW. If WEN is HIGH (inactive) for these 3 clock
cycles, data will not be written in to the previous queue. The write port discrete
full flag will update to show the full status of the newly selected queue (Q
last cycle’s rising edge (“C”). Data present on the data input bus (Din), can be
written into the newly selected queue (Q
third cycle (“D”) following a change of queue, provided WEN is LOW and the
new queue is not full. If the newly selected queue is full at the point of its selection,
any writes to that queue will be prevented. Data cannot be written into a full
queue.
Operation, Figure 11, Write Operations & First Word Fall Through for timing
diagrams and Figure 12, Full Flag Timing in Expansion Mode for timing
diagrams.
0
1
Standard mode operation is defined as individual words will be written to the
Changing queues requires a minimum of 3 WCLK cycles on the write port
Refer to Figure 10, Write Queue Select, Write Operation and Full flag
Device Select
(Compared to
ID0,1,2)
Device Select
(Compared to
ID0,1,2)
5 4 3
5 4 3
WRADD[5:0]
Write Queue Address
(3 bits = 8 Queues)
2
X
2
COMMERCIAL AND INDUSTRIAL
X
1
1
X
) on the rising edge of WCLK on the
6114 drw05
X
0
0
TEMPERATURE RANGES
X
) at this