TDA19989 NXP Semiconductors, TDA19989 Datasheet - Page 10

• Manufacturer Part Number: TDA19989
• Description: 150 MHz pixel rate HDMI 1.3 transmitter
• Manufacturer: NXP Semiconductors

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NXP Semiconductors
Table 4.
TDA19989_1
Preliminary data sheet
External
assignment
Pin
number
F3
F2
F1
G1
G2
G3
H2
H3
C3
C2
D3
D2
D1
E1
E2
E3
A4
B4
A3
B3
A2
B2
B1
C1
Video input swap to VP[23:20]
Pin
name
VPC[7] 000b
VPC[6]
VPC[5]
VPC[4]
VPC[3] 001b
VPC[2]
VPC[1]
VPC[0]
VPB[7] 010b
VPB[6]
VPB[5]
VPB[4]
VPB[3] 011b
VPB[2]
VPB[1]
VPB[0]
VPA[7] 100b
VPA[6]
VPA[5]
VPA[4]
VPA[3] 101b
VPA[2]
VPA[1]
VPA[0]
SWAP_A[2:0]
selector
value
In the same way:
The device expects to receive big endian incoming data. However, in cases where the
input digital stream to the chip is little endian, the use of the mirror bit of the same register
can help to re-order the input bits as described in
•
•
•
•
•
SWAP_B[2:0] is used to map incoming video port to the internal port VP[19:16].
SWAP_C[2:0] is used to map incoming video port to the internal port VP[15:12].
SWAP_D[2:0] is used to map incoming video port to the internal port VP[11:8].
SWAP_E[2:0] is used to map incoming video port to the internal port VP[7:4].
SWAP_F[2:0] is used to map incoming video port to the internal port VP[3:0].
Internal assignment
Internal
port
VP[23]
VP[22]
VP[21]
VP[20]
VP[23]
VP[22]
VP[21]
VP[20]
VP[23]
VP[22]
VP[21]
VP[20]
VP[23]
VP[22]
VP[21]
VP[20]
VP[23]
VP[22]
VP[21]
VP[20]
VP[23]
VP[22]
VP[21]
VP[20]
Rev. 01 — 15 February 2010
RGB
G[7]
G[6]
G[5]
G[4]
G[7]
G[6]
G[5]
G[4]
G[7]
G[6]
G[5]
G[4]
G[7]
G[6]
G[5]
G[4]
G[7]
G[6]
G[5]
G[4]
G[7]
G[6]
G[5]
G[4]
YCbCr
4 : 4 : 4
Y[7]
Y[6]
Y[5]
Y[4]
Y[7]
Y[6]
Y[5]
Y[4]
Y[7]
Y[6]
Y[5]
Y[4]
Y[7]
Y[6]
Y[5]
Y[4]
Y[7]
Y[6]
Y[5]
Y[4]
Y[7]
Y[6]
Y[5]
Y[4]
HDMI 1.3 transmitter with HDCP and CEC support
YCbCr 4 : 2 : 2
semi-planar
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
[11]
[10]
[9]
[8]
[11]
[10]
[9]
[8]
[11]
[10]
[9]
[8]
[11]
[10]
[9]
[8]
[11]
[10]
[9]
[8]
[11]
[10]
[9]
[8]
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
[11]
[10]
[9]
[8]
[11]
[10]
[9]
[8]
[11]
[10]
[9]
[8]
[11]
[10]
[9]
[8]
[11]
[10]
[9]
[8]
[11]
[10]
[9]
[8]
Table
5.
YCbCr 4 : 2 : 2
ITU656
Cb[11]
Cb[10]
Cb[9]
Cb[8]
Cb[11]
Cb[10]
Cb[9]
Cb[8]
Cb[11]
Cb[10]
Cb[9]
Cb[8]
Cb[11]
Cb[10]
Cb[9]
Cb[8]
Cb[11]
Cb[10]
Cb[9]
Cb[8]
Cb[11]
Cb[10]
Cb[9]
Cb[8]
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
[11]
[10]
[9]
[8]
[11]
[10]
[9]
[8]
[11]
[10]
[9]
[8]
[11]
[10]
[9]
[8]
[11]
[10]
[9]
[8]
[11]
[10]
[9]
[8]
TDA19989
© NXP B.V. 2010. All rights reserved.
Cr[10]
Cr[10]
Cr[10]
Cr[10]
Cr[10]
Cr[10]
Cr[11]
Cr[9]
Cr[8]
Cr[11]
Cr[9]
Cr[8]
Cr[11]
Cr[9]
Cr[8]
Cr[11]
Cr[9]
Cr[8]
Cr[11]
Cr[9]
Cr[8]
Cr[11]
Cr[9]
Cr[8]
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
10 of 47
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
[11]
[10]
[9]
[8]
[11]
[10]
[9]
[8]
[11]
[10]
[9]
[8]
[11]
[10]
[9]
[8]
[11]
[10]
[9]
[8]
[11]
[10]
[9]
[8]