TDA7521 ST Microelectronics, TDA7521 Datasheet
TDA7521
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TDA7521 Summary of contents
Page 1
... BD/HF/E/HF/F/HF). Two stereo DACs convert the in- put bitstreams from TDA7522. All the clock signals (for ADCs and DACs) are generated by a low-jitter PLL-based clock manager. All TDA7521’s analog preprocessing is controlled by TDA7522 by means of an UART interface (which imple- 2 ments an I C-like protocol). Housed in a TQFP 44, 10 10mm package, TDA7521 features the functions shown in figure below ...
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... ADCs and output digital multiplexer. The required loop filter network is made 160pF capacitor from FILT to GND_pll in parallel with the series of a 10nF and a 4K resistor. All clock- related setups are communicated to TDA7521 via UART interface. 1.2 Voltage references REFIN is an internal voltage reference generated by a resistor divider between VCC_dac and VSS_dac. Nominal value (with VCC_dac=5V) is REFIN=2.5V. Careful filtering of this pin is essential ...
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... Note: 1. Overflow and Underflow for the HF ADC are latched by a dedicated FSM and read via UART interface. 1.6 DAC section In TDA7521 are present two 3rd order SC smoothing filters to be used in Digital-to-Analog conversion. Its input signal is a bitstream created by a 2nd order digital (1) ...
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... TDA7521 the bitstream is passed to the analog chip and properly processed by the filter. The filter exhibits 96dB SNR and more than -80dB THD for a full scale input signal. 4/11 ...
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... Figure 2. TDA7521 timings in 768 Fs mode Fig.3. A349 timing: (1) External clock ( rising edge, while RF data change on the falling edge); (3.A, 3.B, 3.C, 3.D) Internally generated 96 F clocks for Servo ADC; (4) Servo data IN; (5) Servo data OUT; (6) RF data IN; ( data OUT ...
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... TDA7521 2.0 FEATURE The main performance of TDA7521 are reported below Table 2. Main DC Characteristics (I) Current input A+C diode input B+D diode input E diode input F diode input Table 3. Main DC Characteristics (II) Voltage input A+C diode input B+D diode input E diode input F diode input The polarity of input signals can be defined by ST7 individually Table 4 ...
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... Table 5. AC Main Performances DAC Single end Output Frequency response Dynamic Range THD@Full scale 3.0 PIN FUNCTION TDA7521 is housed quad flat pack package; the related pin list is reported below. Table 6. TDA7521 Pin List Pin Number Name REXT ...
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... TDA7521 Pin Number Name 24 BSR 25 SYNC D1/UF 33 D0/OF 34 GND_ADC 35 VDD_ADC 36 GND_ADC 37 VCC_ADC 38 SCK 39 SDA 40 HFMON VSS_PRE 44 VCC_PRE Notes: 1. Current or Voltage input, DC coupled 2. Precision Resistor connected between Rext and ground 3. These pins are to be left unconnected 4 ...
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... TDA7521 REGISTERS ADDRESS MAP Inside TDA7521 there are 16 registers that are to programmed by TDA7522; table nr.9 report the list. All registers are 8 bit wide. Table 7. TDA7521 registers Map Address 0000 AC Gain reg 0001 BD Gain reg 0010 E Gain reg 0011 F Gain reg 0100 AC Offset Adjustment reg ...
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... TDA7521 TQFP44 - 44 lead Quad Flat Package Symb Min A A1 0.05 A2 1.35 1.40 B 0.30 0.37 C 0.09 D 12.00 D1 10.00 D3 8.00 e 0.80 E 12.00 E1 10.00 E3 8.00 L 0.45 0. Drawing is not to scale. 10/11 mm Typ Max Min 1.60 0.15 0.002 1.45 0.053 0.45 0.012 0.20 0.004 0.75 0.018 3 TQFP4410 inch Typ Max 0.063 0.006 0.055 0.057 ...
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... STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. 1998 STMicroelectronics - All Rights Reserved TDA7521 11/11 ...