STLC5432 ST Microelectronics, STLC5432 Datasheet - Page 21

• Manufacturer Part Number: STLC5432
• Description: 2Mbit CEPT & PRIMARY RATE CONTROLLER DEVICE
• Manufacturer: ST Microelectronics

RDS0/1Receive Data Select Bit 0/1
DOHZ DOUT High Impedance
9.25 CR3 Configuration Register 3
7
LP1
LP2
LP3
1
ASP
When the PRS analyser is validated
SAV = 1 (TCR2), Sequence is checked by
the analyser during the Time Slot(s)
selected by TCR2.
When the PRS generator is validated,
SGV = 1 (TCR1 register), Sequence is
transmitted by the generator during the Time
Slot(s) selected by TCR1.
DOHZ = 1, DOUT pin is high impedance
DOHZ = 0, DOUT pin is in accordance with
TS0E bit of CR5 register.
Loop Back 1
This loop back is the nearestto the line side
pins. If LP1 = 1 incoming data are replaced by
outgoingdata.
If AISX=0, loopback is transparent(outgoing
data is transmitted)
If AISX=1, Alarm Indication Signal is transmitted.
Loop Back 2
Loopback located between the HDB3/BIN
decoderoutput and the BIN/HDB3 encoder
input. Loop back 2 is always transparent.
If LP2 = 1 Data received from the line are
returned to the line.
Loop Back 3
If LP3 = 1 Frames and Multiframes genera-
ted by the emitter are connected instead of
RDS1
RDS1
0
0
1
1
0
1
Nu
After Reset = 80H
RDS0
RDS0
X
X
AISX
0
1
0
1
Sequence is transmitted on
Data Input (DIN pin). Instead
Sequence comes from Data
Input (DIN pin). Sequence is
onto the line. Loopback 1
ALS
Sequence is transmitted
transmitted onto the line.
transmitted onto the line.
Sequence comes from
Sequence comes from
Sequence comes from
Data Out (DOUT pin).
or 3 can be validated.
of sequence, ”1” are
memory Output.
Memory input.
Destination
LP3
Source
LP2
LP1
0
ALS
AISX
ASP
9.26 CR4 Configuration Register 4
7
The first three bits of this register, M 0/2, must not
be changed by the microprocessor if the serial P
is selected, they can be programmed only in par-
allel interface mode. If Serial interface or Stand
Alone mode is chosen, then Multiplexes are at 2
048kb/s and local clock frequency may be either
2 048 kHz or 4 096 kHz.
NB : If parallel micro interface is selected, DOUT
will be valid after writing CR4 Register.
M 0/2 Multiplex DIN and Multiplex DOUT
DCP
DEL
1
EQV
data stream coming from the decoder
HDB3-BIN, just before frame memory input.
Alarm Line Signal to be transmitted.
When this bit is at 1, AIS or APS are
transmitted onto the line.
Alarm Indication signal.
If ALS is at ”1”, and AISX is at ”1”:
Alarm Indication signal (All 1s) is transmit-
ted onto the line.
If ALS is at ”1” and AISX is at ’0”:
Auxiliary pattern (0-1-0-1-0-1...) is transmit-
ted onto the line.
Alternate Single Pulse
If ASP = 1 The L01 andL02 outputsdeliver
pulse every 3.9 microseconds. On theline,
onewill be positive,the next negativeand so on.
M2 = 1
M2 = 0 and M1 = 1
M2 = M1 = 0
Double Clock Pulse
When this bit is at ”1”, local clock frequency
value is twice the data rate value.
Data In are shifted on the second falling
edge of the local clock (LCLK).
When this bit is at ”0”, local clock frequency
and data rate value have same value.
Data in are shifted on the falling edge of the
local clock.
Delayed mode.
AVT
Multiplexes are at 8 192 kb/s. Each
multiplex includes 128 Time Slots.
M0 and M1 indicate the Time Slots
selected by the device.
Multiplexes are at 4 096 kb/s. Each
multiplex includes 64 Time Slots.
M0 indicates the Time Slots selected
by the device.
Multiplexes are at 2 048 kb/s. Each
multiplex includes 32 Time Slots.
After Reset = 80H
DEL
DCP
M2
STLC5432
M1
21/46
M0
0