CY7C4241V-15AXC Cypress Semiconductor Corp, CY7C4241V-15AXC Datasheet
CY7C4241V-15AXC
Specifications of CY7C4241V-15AXC
Available stocks
Related parts for CY7C4241V-15AXC
CY7C4241V-15AXC Summary of contents
Page 1
... CY7C4201V/4211V/4221VCY7C4241V/4251VLow Voltage 256/512/1K/4K/ Synchronous FIFOs Features High-speed, low-power, first-in, first-out (FIFO) memories ■ 256 x 9 (CY7C4201V) ❐ 512 x 9 (CY7C4211V) ❐ (CY7C4221V) ❐ (CY7C4241V) ❐ (CY7C4251V) ❐ High-speed 66-MHz operation (15-ns read/write cycle time) ■ Low power ( mA) ■ CC 3.3V operation for low power consumption and easy integration ■ ...
Page 2
... Width Expansion Configuration...................................... 7 Flag Operation .................................................................. 7 Full Flag....................................................................... 7 Empty Flag .................................................................. 7 Maximum Ratings............................................................. 8 Document #: 38-06010 Rev. *C CY7C4201V/4211V/4221V CY7C4241V/4251V Operating Range............................................................... 8 Electrical Characteristics Over the Operating Range ..... 8 Capacitance ...................................................................... 8 Switching Characteristics Over the Operating Range .... 9 Switching Waveforms .................................................... 10 Ordering Information...................................................... 16 256 x 9 Low Voltage Synchronous FIFO................... 16 512 x 9 Low Voltage Synchronous FIFO ...
Page 3
... The rising edge clocks data into the FIFO when WEN1 is LOW and WEN2/LD is HIGH and the FIFO is not Full. When LD is asserted, WCLK writes data into the programmable flag-offset register. Document #: 38-06010 Rev. *C Figure 2. 32-Pin TQFP CY7C42X1V-15 CY7C42X1V-25 66 CY7C4211V CY7C4221V CY7C4231V 512 Description CY7C4201V/4211V/4221V CY7C4241V/4251V CY7C42X1V-35 Unit 40 28.6 MHz CY7C4241V CY7C4251V Page [+] Feedback ...
Page 4
... HIGH, data can be loaded into the input register and RAM array on the LOW-to-HIGH transition of every write clock (WCLK.) Data is stored in the RAM array sequentially and independently of any on-going read operation. CY7C4241V/4251V pins is written into the FIFO on each outputs. New data will be presented on before RCLK for valid ...
Page 5
... Full Offset (LSB) Reg Full Offset (LSB) Reg Default Value = 007h Default Value = 007h (MSB) 0000 CY7C4241V/4251V shows the register sizes and default Empty Offset (LSB) Reg. Default Value = 007h (MSB Full Offset (LSB) Reg Default Value = 007h 0 ...
Page 6
... FIFO is greater than or equal to CY7C4421V (64 – m), CY7C4201V (256 – m), CY7C4211V (512 – m), CY7C4221V (1K – m), CY7C4231V (2K – m), CY7C4241V (4K – m), and CY7C4251V (8K – m). PAF is set HIGH by the LOW-to-HIGH transition of WCLK when the number of available memory locations is greater than m. ...
Page 7
... REN1 and REN2 synchronized to RCLK, i.e exclusively updated by each rising edge of RCLK. RESET (RS) 9 CY7C42X1V Read Enable 2 (REN2) CY7C4201V/4211V/4221V CY7C4241V/4251V READ CLOCK (RCLK) READ ENABLE 1 (REN1) OUTPUT ENABLE (OE) PROGRAMMABLE (PAE) EMPTY FLAG (EF) #1 EMPTY FLAG (EF) #2 DATA OUT ( Page ...
Page 8
... Test Conditions ° MHz 5. 510Ω GND ≤ Vth = 2.0V . CY7C4201V/4211V/4221V CY7C4241V/4251V Ambient Temperature V CC 3.3V ± 300 mV 0°C to +70°C 3.3V ± 300 mV –40° to +85°C 7C42X1V-25 7C42X1V-35 Unit Min Max Min Max 2.4 2.4 V ...
Page 9
... SKEW2 for Almost-Empty Flag and Almost-Full Flag Notes 9. Pulse widths less than minimum values are not allowed. 10. Values guaranteed by design, not currently tested. Document #: 38-06010 Rev. *C 7C42X1V-15 7C42X1V-25 Min Max Min 66 [10 [10 CY7C4201V/4211V/4221V CY7C4241V/4251V 7C42X1V-35 Unit Max Min Max 40 28.6 MHz ...
Page 10
... CLKL NO OPERATION t REF VALID DATA t OE [12] t SKEW1 , then FF may not change state until the next WCLK rising edge. SKEW1 , then EF may not change state until the next RCLK rising edge. SKEW1 CY7C4201V/4211V/4221V CY7C4241V/4251V NO OPERATION NO OPERATION t WFF REF t OHZ Page [+] Feedback ...
Page 11
... Holding WEN2/LD HIGH during reset will make the pin act as a second enable pin. Holding WEN2/LD LOW during reset will make the pin act as a load enable for the programmable flag offset registers. Document #: 38-06010 Rev. *C [13] Figure 8. Reset Timing RSR RSS t t RSR RSS t t RSS RSR t RSF t RSF t RSF CY7C4201V/4211V/4221V CY7C4241V/4251V [14 OE=0 Page [+] Feedback ...
Page 12
... The Latency Timing applies only at the Empty Boundary (EF = LOW). SKEW1 17. The first word is available the cycle after EF goes HIGH, always. Document #: 38-06010 Rev [16] t FRL t REF [17 OLZ When t < minimum specification, t CLK SKEW1 SKEW1 CY7C4201V/4211V/4221V CY7C4241V/4251V (maximum) = either 2 FRL CLK SKEW1 CLK Page [+] Feedback ...
Page 13
... FRL RCLK t SKEW1 EF REN1, REN2 LOW OE DATA IN OUTPUT REGISTER Q – Document #: 38-06010 Rev. *C Figure 10. Empty Flag Timing t DS DATAWRITE2 t ENS t ENS t t REF REF t A CY7C4201V/4211V/4221V CY7C4241V/4251V t ENH t ENH [16] t FRL t t REF SKEW1 DATA READ Page [+] Feedback ...
Page 14
... Document #: 38-06010 Rev. *C Figure 11. Full Flag Timing NO WRITE SKEW1 DATA WRITE t WFF DATA READ t CLKL t ENH t Note 19 ENH [18] t PAE t ENS CY7C4201V/4211V/4221V CY7C4241V/4251V NO WRITE [11] DATA WRITE t WFF t ENH t ENS t A NEXT DATA READ WORDS Note 20 INFIFO t PAE t t ENS ENH Page [+] Feedback ...
Page 15
... PAF offset = m. 23. 64–m words for CY7C4421V, 256-m words in FIFO for CY7C4201V, 512–m words for CY7C4211V, 1024–m words for CY7C4221V, 2048–m words for CY7C4231V, 4096–m words for CY7C4241V, 8192–m words for CY7C4251V. 24 the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to change during that clock cycle. If the time between the rising edge ...
Page 16
... Package Name 256 x 9 Low Voltage Synchronous FIFO 15 CY7C4201V-15AXC 512 x 9 Low Voltage Synchronous FIFO 15 CY7C4211V-15AI CY7C4211V-15AXI Low Voltage Synchronous FIFO 15 CY7C4221V-15AC Low Voltage Synchronous FIFO 15 CY7C4241V-15AXC Low Voltage Synchronous FIFO 15 CY7C4251V-15AXC 25 CY7C4251V-25AXC Document #: 38-06010 Rev. *C Figure 15. Read Programmable Registers t CLKL t ENH t ...
Page 17
... Package Diagrams Document #: 38-06010 Rev. *C Figure 16. 32-Pin TQFP (7X7X1.0 mm) CY7C4201V/4211V/4221V CY7C4241V/4251V 51-85063 *C Page [+] Feedback ...
Page 18
... Document #: 38-06010 Rev. *C Figure 17. 32-Pin PLCC (.453X.553) in CY7C4201V/4211V/4221V CY7C4241V/4251V 51-85002 *C Page [+] Feedback ...
Page 19
... Fixed empty flag timing diagram Fixed switching waveform diagram typo ESH Added Pb-Free logo to top of front page Inserted industrial temperature range into operating range Added parts CY7C4251V-25AXC, CY7C4251V-15AXC, CY7C4241V-15AXC, CY7C4241V-15JXC, CY7C4241V-25XC, CY7C4231V-25AXC, CY7C4221V-15AI, CY7C4211V-15AXI, CY7C4201V-15AXC to ordering infor- mation. RAME Added Contents ...