CY7C4241V-15AXC Cypress Semiconductor Corp, CY7C4241V-15AXC Datasheet - Page 10

IC SYNC FIFO MEM 4KX9 32-TQFP

CY7C4241V-15AXC

Manufacturer Part Number
CY7C4241V-15AXC
Description
IC SYNC FIFO MEM 4KX9 32-TQFP
Manufacturer
Cypress Semiconductor Corp
Series
CY7Cr
Datasheets

Specifications of CY7C4241V-15AXC

Function
Synchronous
Memory Size
36K (4K x 9)
Data Rate
100MHz
Access Time
10ns
Voltage - Supply
3.3V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
32-TQFP
Configuration
Dual
Density
36Kb
Access Time (max)
11ns
Word Size
9b
Organization
4Kx9
Sync/async
Synchronous
Expandable
Yes
Bus Direction
Uni-Directional
Package Type
TQFP
Clock Freq (max)
66.7MHz
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Supply Current
20mA
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
32
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C4241V-15AXC
Manufacturer:
CY
Quantity:
21
Part Number:
CY7C4241V-15AXC
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Part Number:
CY7C4241V-15AXCT
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Switching Waveforms
Notes
Document #: 38-06010 Rev. *C
REN1,REN2
11. t
12. t
(if applicable)
REN1,REN2
between the rising edge of RCLK and the rising edge of WCLK is less than t
between the rising edge of WCLK and the rising edge of RCLK is less than t
SKEW1
SKEW1
WEN2
Q
D
WCLK
WEN1
WEN1
WEN2
WCLK
RCLK
0
RCLK
0
–Q
–D
OE
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. It the time
FF
EF
8
8
t
ENS
t
OLZ
t
SKEW1
t
ENH
t
t
CLKH
[11]
CLKH
t
t
t
WFF
A
REF
t
OE
Figure 6. Write Cycle Timing
Figure 7. Read Cycle Timing
t
t
CLK
CKL
t
SKEW1
NO OPERATION
[12]
t
DS
t
t
CLKL
CLKL
t
ENS
SKEW1
SKEW1
, then FF may not change state until the next WCLK rising edge.
, then EF may not change state until the next RCLK rising edge.
t
VALID DATA
DH
t
ENH
t
REF
t
WFF
t
CY7C4201V/4211V/4221V
OHZ
NO OPERATION
NO OPERATION
CY7C4241V/4251V
Page 10 of 19
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