CY7C4241V-15AXC Cypress Semiconductor Corp, CY7C4241V-15AXC Datasheet - Page 7

• Manufacturer Part Number: CY7C4241V-15AXC
• Description: IC SYNC FIFO MEM 4KX9 32-TQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C4241V-15AXC

• Function: Synchronous
• Memory Size: 36K (4K x 9)
• Data Rate: 100MHz
• Access Time: 10ns
• Voltage - Supply: 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-TQFP
• Configuration: Dual
• Density: 36Kb
• Access Time (max): 11ns
• Word Size: 9b
• Organization: 4Kx9
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: TQFP
• Clock Freq (max): 66.7MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Supply Current: 20mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

WRITE ENABLE 1 (WEN1)
Width Expansion Configuration
Word width may be increased simply by connecting the corre-
sponding input control signals of multiple devices. A composite
flag should be created for each of the end-point status flags (EF
and FF). The partial status flags (PAE and PAF) can be detected
from any one device.
by using two CY7C42X1Vs. Any word width can be attained by
adding additional CY7C42X1Vs.
When the CY7C42X1V is in a Width Expansion Configuration,
the Read Enable (REN2) control input can be grounded (see
Figure
(WEN2/LD) pin is set to LOW at Reset so that the pin operates
as a control to load and read the programmable flag offsets.
Document #: 38-06010 Rev. *C
PROGRAMMABLE (PAF)
Figure 4. Block Diagram of 64 x 9, 256 x 9, 512 x 9, 1024 x 9, 2048 x 9, 4096 x 9, 8192 x 9 Low-Voltage Synchronous FIFO
WRITE ENABLE 2/LOAD
DATA IN (D)
WRITE CLOCK (WCLK)
). In this configuration, the Write Enable 2/Load
FULL FLAG (FF) # 1
FULL FLAG (FF) # 2
(WEN2/LD)
18
Figure
9
Read Enable 2 (REN2)
demonstrates a 18-bit word width
FF
RESET (RS)
CY7C42X1V
Memory Used in a Width-Expansion Configuration
EF
9
9
Read Enable 2 (REN2)
Flag Operation
The CY7C42X1 devices provide four flag pins to indicate the
condition of the FIFO contents. Empty, Full, PAE, and PAF are
synchronous.
Full Flag
The Full Flag (FF) will go LOW when device is full. Write opera-
tions are inhibited whenever FF is LOW regardless of the state
of WEN1 and WEN2/LD. FF is synchronized to WCLK, i.e., it is
exclusively updated by each rising edge of WCLK.
Empty Flag
The Empty Flag (EF) will go LOW when the device is empty.
Read operations are inhibited whenever EF is LOW, regardless
of the state of REN1 and REN2. EF is synchronized to RCLK,
i.e., it is exclusively updated by each rising edge of RCLK.
FF
RESET (RS)
CY7C42X1V
EF
EMPTY FLAG (EF) #1
EMPTY FLAG (EF) #2
CY7C4201V/4211V/4221V
READ CLOCK (RCLK)
READ ENABLE 1 (REN1)
OUTPUT ENABLE (OE)
PROGRAMMABLE (PAE)
9
DATA OUT (Q)
CY7C4241V/4251V
18
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