74HCT7030D,112 NXP Semiconductors, 74HCT7030D,112 Datasheet - Page 10
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74HCT7030D,112
Manufacturer Part Number
74HCT7030D,112
Description
IC 9X64 FIFO REGISTER 3ST 28SOIC
Manufacturer
NXP Semiconductors
Series
74HCTr
Datasheets
1.74HCT4046ADB112.pdf
(19 pages)
2.74HCT4046ADB112.pdf
(23 pages)
3.74HC7030D652.pdf
(22 pages)
Specifications of 74HCT7030D,112
Function
Asynchronous, Synchronous
Memory Size
576 (9 x 64)
Data Rate
33MHz
Voltage - Supply
4.5 V ~ 5.5 V
Mounting Type
Surface Mount
Package / Case
28-SOIC (7.5mm Width)
Logic Family
HCT
Logical Function
FIFO Register
Number Of Elements
1
Number Of Bits
9
Number Of Inputs
9
Number Of Outputs
9
High Level Output Current
-6mA
Low Level Output Current
6mA
Propagation Delay Time
117ns
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
4.5V
Output Type
3-State
Polarity
Non-Inverting
Technology
CMOS
Frequency (max)
36(Typ)MHz
Mounting
Surface Mount
Pin Count
28
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Quiescent Current
50uA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Operating Temperature
-
Access Time
-
Lead Free Status / Rohs Status
Compliant
Other names
568-2900-5
933798900112
933798900112
Philips Semiconductors
HC TYPES
AC waveforms 74HC
AC waveforms 74HC
March 1988
handbook, full pagewidth
HCMOS family characteristics
(1) In Fig.4 the active transition of the clock is going from LOW-to-HIGH and the active level of the forcing signals (SET, RESET
(2) For AC measurements: t
Fig.4
and PRESET) is HIGH. The actual direction of the transition of the clock input and the actual active levels of the forcing signals
are specified in the individual device data sheet.
Fig.3 Input rise and fall times, transition times and propagation delays for combinatorial logic ICs.
Set-up times, hold times, removal times, propagation delays and the maximum clock pulse frequency for
sequential logic ICs.
OUTPUT
PRESET
CLOCK
RESET,
INPUT
INPUT
INPUT
r
DATA
SET,
= t
f
= 6 ns; when measuring f
handbook, halfpage
INPUT
OUTPUT
10 %
50%
t su
t rem
50%
t r
10%
50%
t PLH
90%
t PHL
t THL
t WH
10%
max
90%
50%
90%
t h
, there is no constraint on t
t r
1/f max
t TLH
50%
90%
t f
50%
10%
10
t WL
t su
t f
t PHL
t PLH
t TLH
r
, t
f
with 50% duty factor.
MGK564
t h
FAMILY SPECIFICATIONS
t THL
V CC
GND
MGK569
V CC
GND
V CC
GND
V CC
GND