HT68F04 Holtek Semiconductor, HT68F04 Datasheet - Page 98

• Manufacturer Part Number: HT68F04
• Description: Small Package Enhanced Flash Type 8-Bit MCU
• Manufacturer: Holtek Semiconductor

·
Rev. 1.00
ADCR1 Register
¨
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2~0
HT66F03/HT66F04
Name
POR
R/W
Bit
ACS4
ACS4: Selecte Internal 1.25V as ADC input Control
This bit enables 1.25V to be connected to the A/D converter. The V125EN bit must first have
been set to enable the bandgap circuit 1.25V voltage to be used by the A/D converter. When the
ACS4 bit is set high, the bandgap 1.25V voltage will be routed to the A/D converter and the other
A/D input channels disconnected.
V125EN: Internal 1.25V Control
This bit controls the internal Bandgap circuit on/off function to the A/D converter. When the bit
is set high the bandgap voltage 1.25V can be used by the A/D converter. If 1.25V is not used by
the A/D converter and the LVR/LVD function is disabled then the bandgap reference circuit will be
automatically switched off to conserve power. When 1.25V is switched on for use by the A/D
converter, a time t
an A/D conversion.
unimplemented, read as ²0²
VREFS: Selecte ADC reference voltage
This bit is used to select the reference voltage for the A/D converter. If the bit is high, then the
A/D converter reference voltage is supplied on the external VREF pin. If the pin is low, then the
internal reference is used which is taken from the power supply pin VDD. When the A/D
converter reference voltage is supplied on the external VREF pin which is pin-shared with other
functions, all of the pin-shared functions except VREF on this pin are disabled.
unimplemented, read as ²0²
ADCK2, ADCK1, ADCK0: Select ADC clock source
These three bits are used to select the clock source for the A/D converter.
R/W
0: Disable
1: Enable
0: Disable
1: Enable
0: Internal ADC power
1: VREF pin
000: f
001: f
010: f
011: f
100: f
101: f
110: f
111: Undefined
7
0
SYS
SYS
SYS
SYS
SYS
SYS
SYS
/8
/64
/2
/4
/16
/32
V125EN
R/W
6
0
BG
should be allowed for the bandgap circuit to stabilise before implementing
¾
¾
¾
5
VREFS
HT66F03/HT66F04/HT68F03/HT68F04
98
R/W
4
0
¾
¾
¾
3
ADCK2
R/W
2
0
ADCK1
R/W
1
0
April 16, 2010
www.DataSheet4U.com
ADCK0
R/W
0
0