83C196EA Intel Corporation, 83C196EA Datasheet - Page 12

• Manufacturer Part Number: 83C196EA
• Description: CHMOS 16-BIT MICROCONTROLLER
• Manufacturer: Intel Corporation

83C196EA CHMOS 16-BIT MICROCONTROLLER — AUTOMOTIVE
8
CLKOUT
CRBUSY#
CRDCLK
CRIN
CROUT
CS2:0#
EA#
EPA16:0
Name
Type
I/O
O
O
O
O
I
I
I
Clock Output
Output of the internal clock generator. The CLKOUT frequency can be
programmed to one of five frequencies: the internal operating frequency (f)
divided by a factor of two, four, eight, or sixteen, or the same frequency as the
oscillator input (F
CLKOUT shares a package pin with P2.7
Code RAM Busy
This signal indicates that the serial debug unit (SDU) is not ready to conduct a
transaction.
Code RAM Clock
Provides the clock signal for the serial debug unit (SDU). The maximum clock
frequency equals the operating frequency (f) divided by two.
Code RAM Data Input
Serial input for test instructions and data into the serial debug unit (SDU). Data
is transferred in 8-bit bytes with the most-significant bit (MSB) first. Each byte is
sampled on the rising edge of CRDCLK.
Code RAM Data Output
Serial output for data from the serial debug unit (SDU). Data is transferred in 8-
bit bytes with the most-significant bit (MSB) first. Each byte is valid on the rising
edge of CRDCLK.
Chip-select Lines 0–2
The active-low output CS x # is asserted during an external memory cycle when
the address to be accessed is in the range programmed for chip select x . If the
external memory address is outside the range assigned to the three chip
selects, no chip-select output is asserted and the bus configuration defaults to
the CS2# values.
Immediately following reset, CS0# is automatically assigned to the range
FF2000–FF20FFH (1F2000–1F20FFH if external).
CS2:0# share package pins with EPORT.7:5.
External Access
This input determines whether memory accesses to special-purpose and
program memory partitions (FF2000–FF3FFFH) are directed to internal or
external memory. These accesses are directed to internal memory if EA# is
held high and to external memory if EA# is held low. For an access to any other
memory location, the value of EA# is irrelevant.
EA# is sampled and latched only on the rising edge of RESET#. Changing the
level of EA# after reset has no effect.
On devices with no internal nonvolatile memory, always connect EA# to V
Event Processor Array (EPA) Capture/Compare Channels
High-speed input/output signals for the EPA capture/compare channels.
EPA16:0 share package pins with the following signals: EPA0/P7.0/T1CLK,
EPA1/P7.1/T1RST, EPA2/P7.2/T2CLK, EPA3/P7.3/T2RST,
EPA4/P7.4/T3CLK, EPA5/P7.5/T3RST, EPA6/P7.6/T4CLK,
EPA7/P7.7/T4RST, EPA8/P8.0, EPA9/P8.1, EPA10/P8.2, EPA11/P8.3,
EPA12/P8.4, EPA13/P8.5, EPA14/P8.6, EPA15/P8.7, and EPA16/P10.4.
Table 4. Signal Descriptions (Continued)
XTAL
1
). CLKOUT has a 50% duty cycle.
Description
ADVANCE INFORMATION
SS
.