LS110GXS-1CF269C Lattice Semiconductor Corp., LS110GXS-1CF269C Datasheet
LS110GXS-1CF269C
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LS110GXS-1CF269C Summary of contents
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... XPIO 110GXS © 2004 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
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Lattice Semiconductor Figure 1. XPIO 110GXS Block Diagram LB_LVDS_Enb RX_LV_EN RX_D_LV_P[0] RX_D_LV_N[ LVDS . Output RX_D_LV_P[15] RX_D_LV_N[15] * RX_CK_LV_P RX_CK_LV_N RX_LV_CKDLY[1:0] SC_LV_ISET[1:0] SC_LSB1STb CK622OUT_P CK622OUT_N LB_P622_Enb TX_D_LV_P[0] TX_D_LV_N[ LVDS TX_D_LV_P[15] Input TX_D_LV_N[15] TX_LV_PLLBPb 0 1 ...
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Lattice Semiconductor The XPIO 110GXS is divided into a transmitter section and a receiver section. The major operations performed by the chip are: Transmitter Operation 1. Low jitter clock generation via the Clock-Multiplier-Unit (CMU) 2. 16-bit LVDS parallel data input ...
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Lattice Semiconductor The FIFO circuitry indicates an overflow or underflow condition by asserting TX_FIFO_ERR high. The TX_FIFO_ERR only provides status information about an overflow or underflow. It does not indicate which of the two events actually occurred. During the period ...
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Lattice Semiconductor The external reference clock is essential for the CDR block. The reference clock provides two functions: One func- tion is training the VCO in the CDR PLL to the serial data-stream frequency. The other is to generate a ...
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Lattice Semiconductor Figure 2. LVDS Loopback Mode Block Diagram LB_LVDS_ENb=0 BIST_ENb=0 BIST_LB_SC0=0 BIST_LB_SC1=1 RX_D_LV[0..15] LVDS Data RX_CK_LV_P/N LVDS Clock Bypass TX_D_LV[0..15] LVDS Data TX_CL_LV_P/N REF_CK_P/N LVDS Line Loopback Line loopback is a diagnostic mode that establishes a parallel connection between ...
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Lattice Semiconductor Mode 2: Synchronous line loopback with clock clean-up. Driving LB_P622_Enb low enables line loopback mode. In order to make this loopback mode SONET/SDH compliant the CK622OUT_P/N must be connected to a VCXO-powered PLL chip (e.g. MAX3670), and CK622OUT_SEL ...
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Lattice Semiconductor Driving RX_REF_CK_P/N is only necessary when: • The transmitter and receiver run at independent data rates • Line Loopback Mode 1 is active • Line Loopback Mode 2 is active Figure 5 shows how a reference clock is ...
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Lattice Semiconductor Figure 7. Differential Oscillator Driving to XPIO 110GXS Clock Input (AC Coupled) Figure 8. LVDS Output and Input Connection LVDS Output Figure 9. External Loop Filter Components 0.01 µF 396Ω TX_FILT_EXTP 0.1µ 50Ω 0.1µF External Zo ...
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Lattice Semiconductor PCB Layout Recommendations The TX/RX filter components should be small form factor capacitors and resistors. They should be placed as close as possible to the XPIO 110 device. The TX filter components should be surrounded by a copper ...
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Lattice Semiconductor Electrical Specifications AC Signaling Definitions Figure 11. Differential Voltage Measurements ICM, OCM V- V+ -V- Figure 12. Rise and Fall Time Measurements Figure 13. LVDS Data to Clock Relationship of Transmitter, 1/16 TX_CK_LV_N, TX_CK_LV_SEL ...
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Lattice Semiconductor Figure 14. LVDS Data to Clock Relationship of Transmitter, 1/32 TX_CK_LV_P, TX_CK_LV_SEL = 0, fclk = 311.04MHz TX_D_LV_P/N[15:0] Figure 15. LVDS Data to Clock Relationship of Receiver RX_D_LV_P/N[15:0] RX_CK_LV_P XPIO 110GXS Data Sheet nd of Frequency (311.04MHz for ...
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Lattice Semiconductor Configuration Pin Descriptions Pin Name State Transmitter Controls TX_D_EN TX_LV_PLLBPb TX_FIFO_INIT TX_CML_ISET[1:0] 1 TX_CK622_PA[1:0] RESET_TXb PWDN_TXb TX_CK_LV_SEL TX_CK_LV_SEL = 1/16 TX_CK_LV_PA[1:0] TX_CK_LV_SEL = 1/32 TX_CP_ISET[1:0] Receiver Controls RX_REF_CK_ENb RX_LV_CKDLY[1:0] 1 TX_D_P/N output is active 0 TX_D_P/N output is ...
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Lattice Semiconductor Configuration Pin Descriptions (Continued) Pin Name State RX_LOS RX_LOS_POL RX_D_RP_ENb 3 RX_LOCK2REFb 3 SC_LOCK_DIFF[1:0] SC_LV_ISET[1:0] RX_LV_EN PWDN_RXb RESET_RXb General Controls CK622OUT_SEL SC_LSB1STb 4 REF_CK_SEL BIST_ENb BIST_LB_SC[1:0] 1. Only available when CK622OUT_SEL = 0 (CMU CLK Mode ...
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Lattice Semiconductor Absolute Maximum Ratings 1.3V Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to ...
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Lattice Semiconductor Electrical Characteristics High Speed Input/Output Specifications Symbol Parameter AC Characteristics t CML output rise time R t CML output fall time F Input reference clock frequency f REFCLK (REF_CK_P/N) Receiver input reference clock frequency (RX_REF_CK_P/N, active only in ...
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Lattice Semiconductor Electrical Characteristics (Continued) Low Speed Input/Output Specifications Symbol Parameter AC Characteristics t LVDS output rise times R t LVDS output fall times F LVDS output data invalid prior to LVDS out- t CQB put clock LVDS output data ...
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Lattice Semiconductor Electrical Characteristics (Continued) Low Speed Input/Output Specifications (Continued) Symbol Parameter LVDS receiver common mode range V ICM (TX_D_LV_P/N[15:0], TX_CK_LV_P/N) LVDS input voltage HIGH V IH (TX_D_LV_P/N[15:0], TX_CK_LV_P/N) LVDS single-ended input voltage swing V IS (TX_D_LV_P/N[15:0], TX_CK_LV_P/N) LVCMOS Input/Output ...
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Lattice Semiconductor Common Pin Assignments and Descriptions Pad Name Pin Description RX analog circuit ground TX analog circuit ground I/O ground 1, 3 GND Logic circuit ground PLL ground High-speed limit amplifier ground High-speed transmitter driver ground VDDAR RX analog ...
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Lattice Semiconductor Output Pin Assignments and Descriptions Pin Name TX_D_N TX_D_P TX_LOCK CK622OUT_N CK622OUT_P RX_CK_LV_P RX_CK_LV_N RX_D_LV_N[15], RX_D_LV_P[15], RX_D_LV_N[14], RX_D_LV_P[14], RX_D_LV_N[13], RX_D_LV_P[13], RX_D_LV_N[12], RX_D_LV_P[12], RX_D_LV_N[11], RX_D_LV_P[11], RX_D_LV_N[10], RX_D_LV_P[10], RX_D_LV_N[9], RX_D_LV_P[9], RX_D_LV_N[8], RX_D_LV_P[8], RX_D_LV_N[7], RX_D_LV_P[7], RX_D_LV_N[6], RX_D_LV_P[6], RX_D_LV_N[5], RX_D_LV_P[5], RX_D_LV_N[4], RX_D_LV_P[4], ...
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Lattice Semiconductor Input and Analog Pin Assignments and Descriptions Pin Name RX_D_P, RX_D_N 10 Gbps CML input. RX_REF_CK_P LVPECL/CML 155/622 MHz reference clock for RX. See RX_REF_CK_N Figure 7. 2 REF_CK_N Transmitter reference clock input, see Figure 7. REF_CK is ...
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Lattice Semiconductor Input and Analog Pin Assignments and Descriptions Pin Name TX_CK_LV_PA[0] LVDS TX clock adjustment for 622 MHz or 311 MHz mode. TX_CK_LV_PA[1] TX_D_EN 10 Gbps CML TX enable. TX_CK622_PA[1] CLK622 timing adjustment. TX_CK622_PA[0] PWDN_TXb TX power down. PWDN_RXb ...
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... LS = Lattice SERDES Device Number 110G = 1 Channel, 10Gbps Standard Support XS = XSBI (for 10G Ethernet) and SFI-4.1 (for OC-192) Ordering Information Part Number Supported Data Rates (Gbps) LS110GXS-1CF269C LS110GXS-2CF269C Part Number Supported Data Rates (Gbps) LS110GXS-1CF269I LS110GXS – X XXXXX X XX Commercial Voltage 9.953 1 ...