LS110GXS-1CF269C Lattice Semiconductor Corp., LS110GXS-1CF269C Datasheet - Page 21

• Manufacturer Part Number: LS110GXS-1CF269C
• Description: Fully Integrated 10gbps Serializer/deserializer Device
• Manufacturer: Lattice Semiconductor Corp.

Input and Analog Pin Assignments and Descriptions
Lattice Semiconductor
RX_D_P, RX_D_N
RX_REF_CK_P
RX_REF_CK_N
REF_CK_N
REF_CK_P
TX_CK_LV_N, TX_CK_LV_P
TX_D_LV_N[15], TX_D_LV_P[15]
TX_D_LV_N[14], TX_D_LV_P[14]
TX_D_LV_N[13], TX_D_LV_P[13]
TX_D_LV_N[12], TX_D_LV_P[12]
TX_D_LV_N[11], TX_D_LV_P[11]
TX_D_LV_N[10], TX_D_LV_P[10]
TX_D_LV_N[9], TX_D_LV_P[9]
TX_D_LV_N[8], TX_D_LV_P[8]
TX_D_LV_N[7], TX_D_LV_P[7]
TX_D_LV_N[6], TX_D_LV_P[6]
TX_D_LV_N[5], TX_D_LV_P[5]
TX_D_LV_N[4], TX_D_LV_P[4]
TX_D_LV_N[3], TX_D_LV_P[3]
TX_D_LV_N[2], TX_D_LV_P[2]
TX_D_LV_N[1], TX_D_LV_P[1]
TX_D_LV_N[0], TX_D_LV_P[0]
RX_FILT_EXTP
RX_FILT_EXTN
TX_FILT_EXTP
TX_FILT_EXTN
RX_REF_CK_Enb
RX_LV_CKDLY[0]
RX_LV_CKDLY[1]
SC_LV_ISET[0]
SC_LV_ISET[1]
RX_LOS
RX_LOS_POL
RX_D_RP_Enb
RX_LOCK2REFb
SC_LOCK_DIFF[1]
SC_LOCK_DIFF[0]
RESET_TXb
LB_P622_Enb
LB_LVDS_Enb
TX_FIFO_INIT
SC_LSB1STb
TX_CML_ISET[1]
TX_CML_ISET[0]
Pin Name
2
10 Gbps CML input.
LVPECL/CML 155/622 MHz reference clock for RX. See
Figure 7.
Transmitter reference clock input, see Figure 7. REF_CK is the
CMU reference clock.
LVDS TX clock, 622 MHz/311 MHz selectable, phase
adjustable.
LVDS data input. See Figure 8.
RX External Filter. See Figure 9.
TX External Filter. See Figure 9.
RX reference clock enable.
LVDS output clock delay programming.
LVDS output current settings.
RX loss of signal. When RX_LOS is asserted, LVDS clock
RX_CK_LV_P/N is driven out, and the LVDS data pins are
muted (i.e. at differential 0).
RX lose signal polarity change.
Receive data repeater enable.
RX PLL lock to reference. The RX PLL locks to the recovered
data clock when this pin is unconnected/pulled high. The RX
PLL locks to either RX_REF_CK or REF_CK depending on the
state of RX_REF_CK_ENb.
Lock indicate frequency resolution settings.
Transmitter reset.
Loopback enabled at parallel 622 MHz port.
Loopback of TX 16b LVDS to RX 16b LVDS.
FIFO initialization.
SERDES LSB 1 first out selection.
CML output current settings.
Pin Description
21
1
XPIO 110GXS Data Sheet
LVCMOS/In
LVCMOS/In
LVCMOS/In
LVCMOS/In
LVCMOS/In
LVCMOS/In
LVCMOS/In
LVCMOS/In
LVCMOS/In
LVCMOS/In
LVCMOS/In
LVCMOS/In
LVCMOS/In
LVCMOS/In
LVPECL/In
CML/In or
Function
LVDS/In
LVDS/In
CML/In
CML/In
CML/In
Analog
Analog
Flip-chip
B17, A17
B16, A16
B15, A15
B14, A14
B13, A13
B12, A12
B11, A11
B10, A10
L15, K15
B9, A9
B8, A8
B7, A7
B6, A6
B5, A5
B4, A4
B3, A3
B2, A2
B1, A1
Ball #
BGA
M14
D17
D15
R13
R16
R17
G12
H11
N13
N15
C13
E17
E15
P13
F11
E12
M4
N1
P1
N4
R7
D3
F9
F2
J5
J1