RF5300 RF Micro Devices, RF5300 Datasheet - Page 3

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RF5300

Manufacturer Part Number
RF5300
Description
LINEAR POWER AMPLIFIER
Manufacturer
RF Micro Devices
Datasheet

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Rev A8 051107
Base
Pkg
Pin
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
VREG1&2
PWR DET
Function
VREG3/
RF OUT
RF OUT
VREG3
RF IN
VCC3
VCC2
VCC1
RFIN
GND
GND
GND
GND
GND
GND
GND
Description
Ground.
RF input. Input is matched to 50Ω and DC block is provided internally.
Same as pin 2.
Ground.
First and second stage input bias. This pin requires a regulated supply
to maintain nominal bias current.
Ground for third stage bias circuit. Attach to RF ground approximately
100mils to ground from package.
Third stage input bias. This pin requires a regulated supply to maintain
a nominal bias current.
Third stage supply bias. This pin is sensitive to bypass capacitors
which should be placed approximately 100mils from package and reso-
nate 5GHz to ground.
Ground.
RF output. Output is matched to 50Ω and DC block is provided.
Same as pin 10.
Ground.
Provides an output voltage proportional to the RF level.
Ground.
Supply voltage for the second stage. Bypass capacitor is needed to
provide isolation from VCC1 and VCC3.
Supply voltage for the first stage.
Ground connection. The backside of the package should be connected
to the ground plane through a short path (i.e., vias under the device will
be required).
Interface Schematic
See pin 2.
See pin 5.
See pin 10.
VREG1
VREG2
RF5300
MATCH
INPUT
VCC2
OUTPUT
MATCH
GND1
BIAS
VCC1
INTERSTAGE
BIAS
MATCH
GND2
BIAS
RF OUT
2-657

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