AN1328 STMicroelectronics, AN1328 Datasheet

AN1328

Manufacturer Part Number

AN1328

Description

I2C COMMUNICATION PROTOCOL WRITTEN IN FUZZYSTUDIOTM4.0 FOR ST52X430

Manufacturer

STMicroelectronics

Datasheet

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1. INTRODUCTION

In this application note we implement two routines to read/write one single byte of data at a time from/into

an EEPROM memory (in this case the ST24x04) using ST52x430 microcontroller. The protocol used to

set up this communication link is the well-known I

ways the micro, while the memory is always the slave.

The procedures can be used with all the ST52 micros and with all the memories compatible with the one

we used for this application. Eventually, some changes have to be done on the software to match different

device characteristics, but due to the program structure flexibility, these are very easy to perform.

The routines were created with

extensions and improvements. Moreover, with some care, they can be imported directly in any user pro-

gram written with

2. THE ST24X04 EEPROM MEMORY

2.1 Functional Description

The ST24x04 is a 4Kbit Electrically Erasable Programmable Memory (EEPROM), organized as 2 blocks

of 256 x8 bits. These devices are compatible with the I

a bi-directional data bus and serial clock. The memories carry a built-in 4 bit, unique device configuration

identification code (1010) corresponding to the I

inputs (E1, E2) so that up to 4 x4K devices may be attached to the I

memories behave as a slave device in the I

serial clock. Read and write operations are initiated by a START condition generated by the bus master.

The START condition is followed by a stream of 7 bits (identification code 1010) plus one read/write bit

and terminated by an acknowledge bit. When writing data to the memory it responds to the 8 bits received

by asserting an acknowledge bit during the 9th bit time. When the data is read by the bus master, it ac-

knowledges the receipt of the data bytes in the same way. Data transfers are terminated with a STOP con-

dition.

In Figure 1 the memory logic diagram is shown. Note that in our application note some functionalities of

the memory are not implemented and, then, some pins are of not concern. For major details refer to the

memory datasheet.

Figure 1. Logic Diagram

Note:WC signal is only available for ST24/25W04 products

December 2000

FUZZYSTUDIO

C COMMUNICATION PROTOCOL WRITTEN IN

MODE/WC

FUZZYSTUDIO

E1-E2

PRE

SCL

4.0 and ready to be used to build up the communication link.

FUZZYSTUDIO™4.0 FOR ST52X430

C protocol with all memory operations synchronized by the

C bus definition. This is used together with 2 chip enable

ST24x04

ST25x04

C (Inter Integrated Circuit), in which the master is al-

4.0 and are easy to be read and structured for future

C standard two-wire serial interface, which uses

APPLICATION NOTE

SDA

C bus and selected individually. The

Author: G. Rascona’

AN1328

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