AN1328 STMicroelectronics, AN1328 Datasheet - Page 3

• Manufacturer Part Number: AN1328
• Description: I2C COMMUNICATION PROTOCOL WRITTEN IN FUZZYSTUDIOTM4.0 FOR ST52X430
• Manufacturer: STMicroelectronics

AN1328 - APPLICATION NOTE
Figure 3. Bus Timing START/STOP
Acknowledge bit (ACK)
An acknowledge signal is used to indicate a successful data transfer. The bus transmitter, either master
or slave, will release the SDA bus after sending 8 bits of data. During the 9th clock pulse period the re-
ceiver pulls the SDA bus low to acknowledge the receipt of the 8 bits of data.
Data Input
During data input the memory samples the SDA bus signal on the rising edge of the clock SCL. Note
that, for correct device operation, the SDA signal must be stable during the clock low to high transition and
the data must change only when the SCL line is low.
Memory Addressing
To start communication between the bus master and the slave ST24x04, the master ST52x430 must ini-
tiate a START condition. Following this, the master sends onto the SDA bus line 8 bits (MSB first) corre-
sponding to the device select code (7 bits) and a R/W bit. The figure 4 below shows the bit format of this
byte called " device selector ".
If a match is found, the corresponding memory will acknowledge the identification on the SDA bus during
the 9th bit time.
Figure 4. Device select byte
2
In figure 5 the fundamentals of I
C protocol is drawn. For the AC timing please refer to the relative
datasheet.
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