AN1328 STMicroelectronics, AN1328 Datasheet - Page 2

• Manufacturer Part Number: AN1328
• Description: I2C COMMUNICATION PROTOCOL WRITTEN IN FUZZYSTUDIOTM4.0 FOR ST52X430
• Manufacturer: STMicroelectronics

AN1328 - APPLICATION NOTE
2.2 Signal Description
As it was said previously, this application note implements the more simple way to set up a communication
between the micro and an EEPROM, letting to the final user an eventual extension of all other functional-
ities this type of memories allow. Below, you will find a brief description of all the signals used in our im-
plementation with no reference to the different modes to write and protect the memory.
Serial Clock (SCL). The SCL input pin is used to synchronize all data in and out of the memory. A resis-
tor can be connected from the SCL line to Vcc acting as a pull up (see Figure 2).
2
Figure 2. Maximum R
Value versus Bus Capacitance (C
) for an I
C Bus
L
BUS
Serial Data (SDA). The SDA pin is bi-directional and is used to transfer data in or out of memory. It is an
open drain output that may be wire-OR’ed with other open drain or open collector signals on the bus. A
resistor must be connected from the SDA bus line to Vcc to act as pull up (see Figure 2).
Chip Enable (E1 - E2). This chip enable inputs are used to set the 2 least significant bits (b2,b3) of the
7-bit device select code. These inputs may be driven dynamically or tied to Vcc or Vss to establish the
device select code. With these two pins, up to 4 memory chips, sharing the same bus, can be addressed.
2
3. I
C BUS BACKGROUND
2
ST24x04 supports the I
C protocol. This protocol defines any device that sends data onto the bus as a
transmitter and any device that reads the data as a receiver . The device that controls the data transfer is
known as the master and the other as the slave . In our case the master will be the microcontroller and it
will always initiate a data transfer and will provide the serial clock for synchronization. The memories are
always slave devices in all communications.
Start condition
START is identified by a high to low transition of the SDA line while the clock SCL is stable in the high
state. A START condition must precede any command for data transfer.
Stop condition
STOP is identified by a low to high transition of the SDA line while the clock SCL is stable in the high state.
A STOP condition terminates communication between the memory and the bus master. A STOP condition
at the end of a READ command, after and only after a NO ACKNOWLEDGE, forces the standby state. A
STOP condition at the end of a WRITE command triggers the internal EEPROM write cycle. Figure 3
shows the bus and clock sequences for START and STOP commands.
2/9