AN1328 STMicroelectronics, AN1328 Datasheet - Page 4

• Manufacturer Part Number: AN1328
• Description: I2C COMMUNICATION PROTOCOL WRITTEN IN FUZZYSTUDIOTM4.0 FOR ST52X430
• Manufacturer: STMicroelectronics

AN1328 - APPLICATION NOTE
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Figure 5. I
C Bus Protocol
Byte Write
Although there are different modes for writing more than one byte into the memory with a single command,
in this example we implemented the Single Byte Write operation. With a few modifications it is then pos-
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sible to get the Multybyte and Page Write operations allowed by the I
C protocol (see the ST24C04
datasheet for further information).
Following a START condition, the master sends a device select code with the R/W bit reset to ’0’. The
memory acknowledges this and waits for a byte address. The byte address of 8 bits provides access to
one block of 256 bytes of the memory. After receipt of the byte address, the device again responds with
an acknowledge.
After that, the master sends one data byte, which is acknowledged by the memory. The master then ter-
minates the transfer by generating a STOP condition. At this point the internal memory program cycle
starts: all inputs are disabled until the completion of this cycle and the memory will not respond to any re-
quest.
Byte Read
Also in this case we have different ways to read the memory content. Here, what has been implemented
is the Random Address Read , that allows to read a byte from a specified memory address. To this aim, a
dummy write is sent to the memory to load the address into the address counter . This is followed by an-
other START condition from the master and the device selector is repeated with the R/W bit set to ’1’. The
memory acknowledges this and outputs the byte addressed. The master has to NOT acknowledge the
byte output, but terminates the transfer with a STOP condition.
The two sequences for Byte Write and Random Byte Read are reported in Figure 6.
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